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1、ZYNQ平台架构及配置平台架构及配置目录一、 ZYNQ平台的硬件架构二、 AXI 协议三、 ZYNQ的部分可重构配置ZYNQ平台的硬件平台的硬件架构架构背景简介背景简介ZYNQ7000系列ARM+FPGA结构XILINX传统FPGA的局限性？ZYNQ平台的硬件架构架构：1、PS（处理器系统）（流程控制等串行设计） 2、PL（可编程逻辑）（并行算法设计）ZYNQ平台的硬件架构PS由四块组成由四块组成：1、APU(应用处理单元)2、内存接口3、IO外设（USB2.0、Ethernet、CAN、SPI、UART、IIC、SD/SDIO、GPIO）4、互连线（APU、IOP和内存单元相互连接，并通过一
2、个多层的AXI互连线与PL连接）ZYNQ平台的硬件架构APU结构1、ACP2、SCU3、Cortex-A9(x2)4、L1 32KB（I/D） 共享L2 512KBZYNQ平台的硬件架构内存接口ZYNQ平台的硬件架构IO外设 RGMII接口ZYNQ平台的硬件架构AXI总线架构AXI_HP 用于PL的四个高性能、高带宽主接口，位宽可配64/32，可访问PS的DDR3控制器和PS的片上RAM资源AXI_GP四个通用接口（两主两从），每个位宽32，可访问PS的DDR3控制器，PS片上RAM资源和其他从设备AXI_ACP用于PL的一个加速一致性主端口，提供快速访问CPU，可选的L1或L2缓存一致性ZY
3、NQ平台的硬件架构PL组成：1、可配置逻辑块(CLB)2、36KB块BRAM3、数字信号处理DSP48E1 Slice4、可编程IO5、时钟管理6、XADCZYNQ平台的硬件架构可编程IOZYNQ平台的硬件架构XADC模块XADC模块ZYNQ平台的硬件架构ZYNQ平台的硬件架构AXI协议AXI4.0是ARM公司提出的AMBA3.0协议的升级版，是一种高性能、高带宽、低延迟的片内总线。AXI协议AXI协议具有如下特点：总线的地址/控制和数据通道是分离的；支持不对齐的数据传输；在突发传输中，只需要首地址；同时具有分离读/写数据通道；更加容易进行时序收敛。通道介绍AXI接口具有5个独立通道：写地址通
4、道（Writeaddresschannel，AW）；写数据通道（Writedatachannel，W）；写响应通道（Writeresponsechannel，B）；读地址通道（Readaddresschannel，AR）；读数据通道（Readdatachannel，R）；每个通道都是一个独立的AXI握手协议。READY/VALID握手机制每个通道都有一对VALID/READY信号发送方用VALID指示什么时候数据或控制信息是有效的；接收方用READY指示可以接收数据或控制信息。传输发生在VALID和READY信号同时为高的时候。通道之间的关系：各个通道都可以独立握手，相互之间的关系是灵活的；读
5、数据必须总是跟在与其数据相关联的地址之后；写响应必须总是跟在与其相关联的写交易的最后出现。READY/VALID握手机制读交易中的握手之间的依赖关系写交易中的握手之间的依赖关系读交易过程写交易过程读猝发交易读猝发交易过程中典型信号的交互过程写猝发交易写猝发交易过程中典型信号的交互过程重叠猝发交易重叠猝发交易过程中典型信号的交互过程AXI互联AXI互联结构模型包括：直通模式只转换模式N-1互联模式1-N互联模式N-M互联模式互联模式直通模式只转换模式N-1互联模式1-N互联模式N-M互联模式共享写和读地址仲裁结构N-M互联模式稀疏互联写和读数据通道Partial Reconfiguration
6、in ZynqBased on modulesBased on diversitiesPartial Reconfiguration in ZynqWhat Problems Does It Solve?System cost, size, and power constraints Multiplex hardware functions Evolving protocol and industry standards Reprogramability as standards evolve Mission critical uptime Update on the fly while sy
7、stem still running Long design implementation cycle times Accelerate development with focus on reconfigurable partitionSome TerminologyReconfigurable Partition (RP) The physical location of FPGA resources selected for partial reconfiguration Static logic Everything but the RP(s) The part of the desi
8、gn that doesnt change Reconfigurable Module (RM) Logic that lives in the RP Defined by hardware interfaces and ports Functional variants for associated RP Different protocol, task, filter, etc. Design FlowStructure the design Separate functions into hierarchical blocks Identify functions to be made
9、into partitions Identify set of signals that will become RP interfaceDesign Flow Synthesize Bottom-up Static “top” and RMs synthesized seperatelyDesign FlowAssemble static design with RM variants RMs replace black boxes in static “top”Design FlowFloorplan the RPs and run DRCs Define regions and logi
10、c resources to be includedDesign FlowImplementation Configurations for static logic and all reconfigurable modules Repeat for all modulesDesign FlowVerify all configurations Ensure that static portions match identicallyDesign Considerations Vivado stores design data in checkpoints Save full design a
11、s a configuration checkpoint for bitstream creation RMs can also be stored as their own checkpoints Save static-only checkpoint to be reused across multiple configurations Routed static checkpoint can remain open in memory Results are locked at the routing level Design Considerations Design Consider
12、ations Partition Pins are junctions between static and reconfigured logic Interface wires can be broken at interconnect tile site Anchor mid-route between static and reconfigurable logic No overhead at reconfigurable partition interface Design Considerations Not Everything Can Be Reconfigured Components CANNOT be reconfigured Clocking resources BUFG, BUFR, MMCM, PLL, etc. I/O resources ISERDES, OSERDES, IDELAYCTRL, etc. MGTs and related components
