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1、( (内存基本知识内存基本知识)-DRAM)-DRAM工工作原理作原理Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDynamic Random Access MemoryEach cell is a capacitor + a transistorVery small sizeSRAM uses six transistors per cellDivided into banks, rows & columnsEach bank can be independently controlledDRAMRamaxe
2、l Technology LimitedRamaxel Technology LimitedConfidentialMain MemoryEverything that happens in the computer is resident in main memoryCapacity: around 100 Mbyte to 100 Gbyte Random access Typical access time is 10- 100 nanosecondsWhy DRAM for Main Memory ? Cost effective (small chip area than SRAM)
3、 High Speed(than HDD, flash) High Density(Gbyte) Mass Production Main memoryRamaxel Technology LimitedRamaxel Technology LimitedConfidentialNotation: K, M, G In standard scientific nomenclature, the metricmodifiers K, M, and G to refer to factors of 1,000,1,000,000 and 1,000,000,000 respectively. Co
4、mputer engineers have adopted K as thesymbol for a factor of 1,024 (210 ) K: 1,024 (210 ) M: 1,048,576 (220 ) G: 1,073,741,824 (230 ) DRAM density 256M-bit 512M-bitRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM DensityRamaxel Technology LimitedRamaxel Technology LimitedConfiden
5、tialWhat is a DRAM? DRAM stands for Dynamic Random Access Memory. Random access refers to the ability to access any of the information within the DRAM in random order. Dynamic refers to temporary or transient data storage.Data stored in dynamic memories naturally decays over time.Therefore, DRAM nee
6、d periodic refresh operation to prevent data loss.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialMemory: DRAM position Semiconductor memory device ROM: Non volatile Mask ROM EPROM EEPROM Flash NAND: low speed, high density NOR: high speed, low density RAM: Volatile DRAM: Dynamic Ran
7、dom Access Memory SRAM: Static Random Access Memory Pseudo SRAMRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Trend : Future HighSpeed- DDR(333MHz500MHz), DDR2(533800Mbps), DDR3(8001600Mbps)- Skew-delay minimized circuit/logic : post-charge logic, wave-pipelining- New Architect
8、ure : multi-bank structure, high speed Interface LowPower- 5.5V = 3.3V(sdr) = 2.5V(ddr) = 1.8V(ddr2) = 1.5v (ddr3) = 1.2v?- Small voltage swing I/O interface : LVTTL to SSTL, open drain- Low Power DRAM(PASR, TCSR, DPD) HighDensity- Memory density: 32MB = 64MB = . 1GB = 2GB = 4GB- application expansi
9、on : mobile, memory DB for shock (than HDD)- Process shrink :145nm(03) =120nm(04) = 100nm = 90nm = 80nm OtherTrends- Cost Effectiveness, Technical Compatibility, Stability, Environment. ReliabilityRamaxel Technology LimitedRamaxel Technology LimitedConfidentialStatic RAMSRAMBasic storage element is
10、a 4 or 6 transistor circuit which will hold a 1 or 0 as long as the system continues to receive powerNo need for a periodic refreshing signal or a clockUsed in system cacheFastest memory, but expensiveSRAMElementEnableLine/BitLineBitLineRamaxel Technology LimitedRamaxel Technology LimitedConfidentia
11、lDynamic RAMDRAMDenser type of memoryMade up of one-transistor (1-T) memory cell which consists of a single access transistor and a capacitorCheaper than SRAMUsed in main memoryMore complicated addressing schemeDRAMCellWordLineBitLineRamaxel Technology LimitedRamaxel Technology LimitedConfidentialRe
12、fresh in DRAMsCapacitor leaks over time, the DRAM must be “REFRESHED”. DRAMCellWordLineBitLineCapacitanceLeakageRamaxel Technology LimitedRamaxel Technology LimitedConfidentialSRAM vs. DRAMRamaxel Technology LimitedRamaxel Technology LimitedConfidentialRamaxel Technology LimitedRamaxel Technology Li
13、mitedConfidentialDRAMLeadFrameandWirebondingRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAMArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidentialSDRAM has the multi bank architecture.Conventional DRAM was product that have single bank architecture.The bank
14、is independent active. memory array have independent internal data bus that have same width as external data bus.Every bank can be activating with interleaving manner.Another bank can be activated while 1st bank being accessed. (Burst read or write)MultiBankArchitectureRamaxel Technology LimitedRama
15、xel Technology LimitedConfidentialDRAMMultiBankArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAMSingleBankArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidentialRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAMBlockDiagram(1)Rama
16、xel Technology LimitedRamaxel Technology LimitedConfidentialDRAMBlockDiagram(2)Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAMCoreArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAMAddressRamaxel Technology LimitedRamaxel Technology LimitedConfidenti
17、alDRAMCoreArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidential16bitDRAMCoreRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAMDataPathRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM1T-1CstructureRamaxel Technology LimitedRamaxel Technolog
18、y LimitedConfidentialuRAS: row address strobeuCAS: column address strobeuWE: write enableuAddress: code to select memory cell locationuDQ (I/O): bidirectional channel to transfer and receive datauDRAM cell: storage element to store binary data bituRefresh: the action to keep data from leakageuActive
19、: sense data from DRAM celluPre charge: standby stateDRAMKeywordRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM cell array consist of so many cells.One transistor & One capacitorSmall sense amplifierLow input gain from charge sharingCS : Small storage capacitor: 25fFCBL : Large
20、parasitic capacitor: over 100fFVc: Storage voltageVCP : half Vc for plate biasVBLP : half Vc for BL pre charge bias(initial bias)DRAMCellRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Array OverviewSimplified ExampleRamaxel Technology LimitedRamaxel Technology LimitedConfidenti
21、alActivating a RowActivating a RowMust be done before a read or writeJust latch the row address and turn on a single wordlineRamaxel Technology LimitedRamaxel Technology LimitedConfidentialWritingWritingA row must be activeSelect the column addressDrive the data through the column muxStores the char
22、ge on a single capacitorRamaxel Technology LimitedRamaxel Technology LimitedConfidentialReadingReadingA row must be activeSelect the column addressThe value in the sense-amplifier is driven back outRamaxel Technology LimitedRamaxel Technology LimitedConfidentialThe Sense-AmplifierSense-AmplifierA pa
23、ir of cross-coupled invertersBasically an SRAM elementWeaker than the column muxWrite data will “outmuscle” the sense-amplifierKeeps the data at full levelRamaxel Technology LimitedRamaxel Technology LimitedConfidentialPrechargePrechargeInactive state (no wordlines active)Precharge control line high
24、Ties the two sides of the sense-amp togetherThis makes the bitlines stay at VDD/2Only stable as long as the precharge control line is highotherwise this is unstable!No capacitors connectedRamaxel Technology LimitedRamaxel Technology LimitedConfidentialActivation RevisitedActivationTurn off the prech
25、arge control lineMakes the sense-amp unstableit wants to go to either 0 or 1 instead of staying at VDD/2A very very very short time later, turn on the wordline of the row to be activated.Couples the capacitor onto the bitlinesThis “tips” the bitlines to hold the stored value.The sense-amp amplifies
26、the capacitor back to full value. (hence the name!)Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM RefreshBecause the stored memory value is stored on a capacitor (that has resistive leakage), the memory is constantly “forgetting” its contents.Eventually, the charge on the capac
27、itor wont be enough to tip the sense-amp in the right direction.But, activating a row restores the cells on that row to their full value.There is an explicit refresh command that just activates and immediately deactivates a row.The DRAM has an internal counter that contains the next row to be refres
28、hed and increments every time a refresh command is issued.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM RefreshData Retention Time DRAM Cell consists of capacitance which has leakage as time Retention time is period for maintaining its data especially 1 data Usually, DRAM Cell
29、 refresh period is 64msRefresh Timing tREF : Real cell retention time (Device characteristic), ex) 90ms(Hot) tRFC : Refresh command operating time, ex) 75nsRefresh Spec. Burst Refresh : 64ms Distribute refresh- 128Mb device (12 Row address) : 64ms / 4K = 15.6us- 256Mb device (13 Row address) : 64ms
30、/ 8K = 7.8usRamaxel Technology LimitedRamaxel Technology LimitedConfidentialAUTO Refresh When this command is input from the IDLE state, the synchronous DRAM starts autorefresh operation. During the auto-refresh operation, refresh address and bank select address are generated inside the Synchronous
31、DRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 8192times are required to refresh the entire memory. Before executing the auto-refresh command, all the bank must be IDLE state. In addition, since the Precharge for all bank is automatically performed after au
32、to-refresh, no Precharge command is required after auto-refresh.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialSelf Refresh Self-Refresh EntrySELF : When this command is input during the IDLE state, the Synchronous DRAM starts self-refresh operation. After the execution of this comm
33、and, selfrefresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary. Self-Refresh ExitSELFX : When this command is executed during self-refresh mode, the Sync DRAM can exit from self-refresh mode. After exiting from s
34、elf-refresh mode, the Sync DRAM enters the IDLE state., no Precharge command is required after auto-refresh.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialMode RegisterSpecial command to initialize the DRAMBurst lengthInterleavingCAS Latency (read command to read data in clocks)For
35、DDR, DLL reset is also hereRamaxel Technology LimitedRamaxel Technology LimitedConfidentialMRS Block DiagramRamaxel Technology LimitedRamaxel Technology LimitedConfidentialMode RegisterBecause the stored memory value is stored on aRamaxel Technology LimitedRamaxel Technology LimitedConfidentialExten
36、ded Mode RegisterSpecial command to initialize DDR DRAMDDR onlydont use for SDRDLL EnableDrive StrengthRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM InterfaceCommand SignalsCAS#, RAS#, WE#, CS#CS# + CAS# = ReadCS# + WE# + CAS# = WriteCS# + RAS# + CAS# = RefreshCS# + RAS# = Act
37、ivateCS# + WE# = Burst StopCS# + WE# + RAS# = PrechargeCS# + WE# + CAS# + RAS# = MRS or EMRSAll others: NOPOther signals:CLK, DATA , DQSRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM InterfaceAll signals go from the host to the memory except DQS and data which are bi-directiona
38、l.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialRead CycleTypical Read CycleBurst Length 4CAS Latency = 3Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialWrite CycleTypical Write CycleBurst Length 4Write latency is always zeroRamaxel Technology LimitedRamaxel Technol
39、ogy LimitedConfidentialData ClockingCLK is always driven by the hostDQS is driven by whoever is driving the dataNV chip drives on write cyclesMemory chip drives on read cyclesThis scheme is called “source-synchronous clocking”Eliminates a lot of the timing headaches from SDRAdds marginRamaxel Techno
40、logy LimitedRamaxel Technology LimitedConfidentialLatenciesAll kindsActivate to PrechargeLast write data to prechargeActivate to ReadActivate to WriteRefresh cycle timeRefresh intervalMinimum row active timeYadda yadda yaddaControlled by PFB_TIMING0, PFB_TIMING1, PFB_TIMING2Ramaxel Technology Limite
41、dRamaxel Technology LimitedConfidentialWrite CycleRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDLLsA DLL is a Delay-Locked LoopNo transistor can switch in zero time, so there will be a delay between clock and DQS on readsBut, it would make it easier if DQS was always in phase with
42、 clock.DLL-off clock-DQS delay not in the specVaries between memory vendorsRe-creates a delayed version of its input clockKeeps DQS on reads aligned with clocksIts an analog circuit and is sensitive to noiseCan lose lock on the input clock if the signal is not clean or the DLL power supply is noisy.
43、Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDLLsDLL onDLL offRamaxel Technology LimitedRamaxel Technology LimitedConfidential tAA, tAC, tOH tRCD, tRP Set-up / Hold time Vih, Vil Voh, Vol Ioh, IolTimingParametersRamaxel Technology LimitedRamaxel Technology LimitedConfidentialSDRAM
44、TimingDiagramRamaxel Technology LimitedRamaxel Technology LimitedConfidentialtAA,tAC,tOH(SDRAM)Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialSetup/holdtime Timing for latching data in Input buffer CLK rising edge is strobe for data ( SDRAM ) DQS rising & falling edge is strobe for
45、data(DDR SDRAM) During Setup & time, there is no abnormal signal allowedRamaxel Technology LimitedRamaxel Technology LimitedConfidentialVIH/VILRamaxel Technology LimitedRamaxel Technology LimitedConfidentialVOH/VOLRamaxel Technology LimitedRamaxel Technology LimitedConfidentialIOH/IOLRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDCSpecRamaxel Technology LimitedRamaxel Technology LimitedConfidentialThanks!结束语结束语谢谢大家聆听！谢谢大家聆听！63
