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1、0202集成电路工艺和版图设集成电路工艺和版图设计计( (参考参考) )微电子制造工艺8/17/20242Jian FangIC常用术语园片：硅片芯片(Chip, Die)：6、8 ：硅（园）片直径：1 25.4mm6150mm; 8200mm; 12300mm; 亚微米1m的设计规范深亚微米 0反型层 沟道源（Source）S漏（Drain）D栅（Gate）G栅氧化层厚度：50埃1000埃（5nm100nm）VT阈值电压电压控制N N沟沟MOSMOS（NMOSNMOS） P型衬底，受主杂质； 栅上加正电压，表面吸引电子，反型，电子通道； 漏加正电压，电子从源区经N沟道到达漏区，器件开通。8/
2、17/202421Jian FangN衬底p+p+漏源栅栅氧化层场氧化层沟道P P沟沟MOSMOS（PMOSPMOS）GDSVTVGSID+-VDS 0 N型衬底，施主杂质，电子导电； 栅上加负电压，表面吸引空穴，反型，空穴通道； 漏加负电压，空穴从源区经P沟道到达漏区，器件开通。8/17/202422Jian FangCMOS CMOS：Complementary Symmetry Metal Oxide Semiconductor 互补对称金属氧化物半导体特点：低功耗VSSVDDVoViCMOS倒相器PMOSNMOSI/OI/OVDDVSSCCCMOS传输门8/17/202423Jian
3、FangN-SiP+P+n+n+P-阱DDVoVGVSSSSVDDCMOS倒相器截面图CMOS倒相器版图8/17/202424Jian FangpwellactivepolyN+ implantP+ implantomicontactmetalA NMOS Example8/17/202425Jian FangpwellPwellActivePolyN+ implantP+ implantOmicontactMetal8/17/202426Jian FangNtype SiSiO2光刻胶光刻胶光光MASK Pwell8/17/202427Jian FangNtype SiSiO2光刻胶光刻胶光
4、刻胶光刻胶MASK Pwell8/17/202428Jian FangNtype SiSiO2光刻胶光刻胶光刻胶光刻胶SiO28/17/202429Jian FangNtype SiSiO2SiO2Pwell8/17/202430Jian FangpwellactivePwellActivePolyN+ implantP+ implantOmicontactMetal8/17/202431Jian FangNtype SiSiO2PwellSiO2光刻胶光刻胶MASK activeMASK ActiveSi3N48/17/202432Jian FangNtype SiSiO2PwellSiO2
5、光刻胶光刻胶光刻胶光刻胶MASK activeMASK ActiveSi3N48/17/202433Jian FangNtype SiSiO2PwellSiO2光刻胶光刻胶光刻胶光刻胶Si3N48/17/202434Jian FangNtype SiSiO2PwellSiO2场氧场氧场氧场氧场氧场氧PwellPwellSi3N48/17/202435Jian FangNtype SiSiO2Pwell场氧场氧场氧场氧场氧场氧PwellPwell8/17/202436Jian FangNtype SiSiO2PwellSiO2场氧场氧场氧场氧场氧场氧PwellPwellpoly8/17/2024
6、37Jian FangactivepwellpolyPwellActivePolyN+ implantP+ implantOmicontactMetal8/17/202438Jian FangNtype SiSiO2PwellSiO2MASK poly场氧场氧场氧场氧场氧场氧PwellPwellpoly光刻胶光刻胶8/17/202439Jian FangNtype SiSiO2PwellSiO2MASK poly场氧场氧场氧场氧场氧场氧PwellPwell光刻胶光刻胶poly8/17/202440Jian FangNtype SiSiO2PwellSiO2场氧场氧场氧场氧场氧场氧PwellPw
7、ellpoly8/17/202441Jian FangNtype SiSiO2PwellSiO2场氧场氧场氧场氧场氧场氧PwellPwellpoly8/17/202442Jian FangactivepwellpolyN+ implantPwellActivePolyN+ implantP+ implantOmicontactMetal8/17/202443Jian FangNtype SiSiO2PwellSiO2MASK N+场氧场氧场氧场氧场氧场氧PwellPwellpoly光刻胶光刻胶8/17/202444Jian FangNtype SiSiO2PwellSiO2场氧场氧场氧场氧场氧
8、场氧PwellPwell光刻胶光刻胶polyN+ implantS/D8/17/202445Jian FangactivepwellpolyP+ implantPwellActivePolyN+ implantP+ implantOmicontactMetal8/17/202446Jian FangNtype SiSiO2PwellSiO2MASK N+场氧场氧场氧场氧场氧场氧PwellPwellpoly光刻胶光刻胶光光S/D8/17/202447Jian FangNtype SiSiO2PwellSiO2场氧场氧场氧场氧场氧场氧PwellPwellS/Dpoly光刻胶光刻胶P+ implan
9、tP+ 接触8/17/202448Jian FangNtype SiSiO2PwellSiO2场氧场氧场氧场氧场氧场氧PwellPwellpolyS/DP+ 接触8/17/202449Jian FangactivepwellpolyP+ implantN+ implantomicontactPwellActivePolyN+ implantP+ implantOmicontactMetal8/17/202450Jian FangNtype SiSiO2PwellSiO2MASK Omicontact场氧场氧场氧场氧场氧场氧PwellPwellpolyS/DP+ 接触8/17/202451Jia
10、n FangactivepwellpolyN+ implantomicontactmetalPwellActivePolyN+ implantP+ implantOmicontactMetal8/17/202452Jian FangNtype SiSiO2PwellSiO2MASK metal场氧场氧场氧场氧场氧场氧PwellpolyS/DP+ 接触metalmetalmetal8/17/202453Jian FangpwellactivepolyN+ implantP+ implantomicontactmetal8/17/202454Jian Fang双极型IC及工艺NPN基极集电极发射极
11、PNP基极集电极发射极CBEIBICIECBEIBICIENPN晶体管晶体管PNP晶体管晶体管8/17/202455Jian FangVCEiCiBVCE(sat)iR双极型晶体管输出特性放大区饱和区 电流放大能力； 电流驱动；8/17/202456Jian Fang基极基极发射极发射极N+N-PN+集电极基极发射极P+NNPEBBCCNCCBBEPPPPNN8/17/202457Jian Fang BiCMOS: 双极(Bipolar)与CMOS相容技术。 BiCMOS可以将双极器件与CMOS器件制作在同一芯片上，使之具有双极电路的高速度、高驱动能力、高模拟精度，又具有CMOS电路的低功耗、
12、高集成度等特性。 BiCMOS工艺较之CMOS工艺和双极工艺都复杂，制作周期长，产品成品率比CMOS低，成本比CMOS高。 高性能双极工艺与CMOS的VLSI工艺80的工艺是相同的，在CMOS生产线上，只要改动或增添一部分工序，增添一部分设备，就可以制作BiCMOS芯片。BiCMOS8/17/202458Jian Fang版图设计（layout）及相关技术8/17/202459Jian FangCell development (Analog/digital)Analog designSchematic entry (transistor symbols)Analog simulation (
13、SPICE models)Layout (layer definitions)Design Rule Checking, DRC ( design rules)Extraction (extraction rules and parameters)Electrical Rule Checking, ERC (ERC rules)Layout Versus Schematic, LVS ( LVS rules)8/17/202460Jian FangLayoutDrawing geometrical shapes: Defines layout hierarchy Defines layer m
14、asksRequires detailed knowledge about CMOS technologyRequires detailed knowledge about design rules (hundreds of rules)Requires detailed knowledge about circuit designSlow and tediousOptimum performance can be obtained8/17/202461Jian Fang图形层的定义图形层的定义N+ implantmetalpwellactivePoly定义若干图层定义若干图层,每层对应一张掩
15、膜版每层对应一张掩膜版pwellactivepolyN+ implantP+ implantomicontactmetal8/17/202462Jian FangLib A Lib B Lib C Cell 1 Cell 2 Cell 3 Tech inst 1 inst 2 Inst 3 版图库的组织版图库的组织 一个库对应一个特定的工艺 针对该工艺的设计规则,和环境设定放在Tech文件中. 一个库可以包含若干不同层次的Cell.8/17/202463Jian Fang版图数据交换文件版图数据交换文件 GDSII格式 CIF格式 EDIF格式基本图形基本图形基本操作基本操作8/17/2024
16、64Jian FangDRC Design Rule Check Checks geometrical shapes: width, length, spacing, overlap, etc.1.单层规则该规则包括各层的最小宽度a及同层间距b 层名称名称宽度度a间距距b层名称名称宽度度a间距距bn+保护环510p+注入区105有源区1010多晶硅布线88p+保护环510多晶硅栅68欧姆孔814布线铝条1010p阱11014电源、地线铝条2510n+注入区105p+墙58/17/202465Jian FangCMOS电路路规则2. 层间规则（包括各层间的间距、包围、迭搭的大小）层间规则（包括各
17、层间的间距、包围、迭搭的大小）8/17/202466Jian Fang 说明 标号 尺寸（um） 有源区包围欧姆孔 a 4 金属（铝）包围欧姆孔 b 3 多晶硅包围欧姆孔 c 4 n+、p+注入区包围有源区 d 5 n+、p+保护环有源区 e 10 n+、p+保护环宽度 f 5 nmos、pmos多晶硅栅宽度 g 6 多晶硅栅伸出有源区 h 12 多晶硅栅与n+、p+保护环迭搭 i 2 多晶硅栅铝布线 j 1 p阱包围p+保护环 k 2 .8/17/202467Jian FangDRC文件例子(片断)(drc metal (width 1.00) (drc metal (sep 0.80) (
18、drc metal omicont (enc 0.30) (drc poly omicont (enc 0.40) 8/17/202468Jian FangEXTRACT用图层间的相对关系判定器件及相互连接关系.例如:Poly跨过Active,即同时出现Poly和Active表明有一个MOS器件.Extracts electrical circuit: transistors, connections, capacitance, resistanceINOutVddGnd8/17/202469Jian FangEXTRACT文件例子(片断)(extractDevice ngate (poly
19、G) (nsd S D) (pwell1 B) nmos4 symbol analogLib )(extractDevice pgate (poly G) (psd S D) (sub B) pmos4 symbol analogLib ) pgateWidth=measureParameter(length (pgate coincident poly) 0.5)pgateLength=measureParameter(length (pgate inside poly) 0.5)saveParameter(pgateWidth W)saveParameter(pgateLength L)
20、ngateWidth=measureParameter(length (ngate coincident poly) 0.5)ngateLength=measureParameter(length (ngate inside poly) 0.5)saveParameter(ngateWidth W)saveParameter(ngateLength L)8/17/202470Jian FangLVS10101010101040EXTLVSLayout versus schematic transistors: parallel or serial Compares electrical cir
21、cuits: (schematic and extracted layout)8/17/202471Jian FangERC Electrical rule check Checks electrical circuit: unconnected inputsshorted outputscorrect power and ground connection8/17/202472Jian FangDigital designBehavioral simulation.Simulation/timing verification with estimated back-annotationPla
22、ce and route (place and route rules)Design Rule Check, DRC (DRC rules)Loading extraction (rules and parameters)Simulation/timing verification with real back-annotationDesign export.8/17/202473Jian FangPlace and RouteGenerates final chip from gate level netlistGoals:Minimum chip sizeMaximum chip spee
23、d.Placement:Placing all gates to minimize distance between connected gatesFloor planning tool using design hierarchySpecialized algorithms ( min cut, simulated annealing, etc.)Timing drivenManual interventionVery compute intensiveHierarchy based floor planningSimulated annealingHigh temperature:move
24、 gates randomlyLow temperature:Move gates locallyMin cutKeep cutting designinto equal sized piecesFor each cut:Move gates arounduntil minimum connectionacross cut8/17/202474Jian FangRouting:Channel based: Routing only in channels between gates (few metal layers: 2)Channel less: Routing over gates (m
25、any metal layers: 3 - 6)Often split in two steps:Global route:Find a coarse route depending on local routing densityDetailed route:Generate routing layoutChannel basedChannel less8/17/202475Jian FangPerformance of sub-micron CMOS ICs are to a large extent determined by place & route.Loading delays b
26、igger than intrinsic gate delaysWire R-C delays becomes important in sub-micronClock distribution over complete chip gets critical at operating frequencies above 100Mhz.Number of wiresWire lengthLocal connectionsGlobal connectionsDelayTechnology1.0u0.5u0.25u0.1u25ps50ps100ps200psGate delayWire load
27、delay8/17/202476Jian Fang8/17/202477Jian Fang8/17/202478Jian Fang8/17/202479Jian Fang集成电路设计（物理层）8/17/202480Jian Fang8/17/202481Jian Fang8/17/202482Jian Fang8/17/202483Jian Fang8/17/202484Jian Fang8/17/202485Jian Fang8/17/202486Jian Fang8/17/202487Jian Fang参考文献参考文献:清华大学出版社清华大学出版社 朱正涌朱正涌 清华大学出版社清华大学出版社 杨之廉杨之廉 8/17/202488Jian FangOVER8/17/202489Jian Fang
