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1、Maximum delay: tpLH=tpHL=15 nstp = 3tpLH + 3tpHL= 315 + 315= 90 ns6. 974LS00:6.20 (a) 6.20 (b) F6.20 (b) ACB(c) DCBAVCCF(d)WVCCZYXZYXF(e)FGYXWVCC(f)CBACEDFG6.21Both halves of the 139 are enabled simultaneously when EN_L is asserted. Therefore, two three-state drivers will be enabled to drive SDATA a
2、t the same time. Perhaps the designer forgot to put an extra inverter on the signal going to 1G or 2G, which would ensure that exactly one source drives SDATA at all times.6.38 十进制译码器的设计十进制译码器的设计输入：四位输入：四位 D、C、B、A，BCD码码输出：十位输出：十位 Y0Y9，十中取一码十中取一码DCBADCBAY0Y0Y1Y1Y2Y2Y3Y3Y4Y4Y5Y5Y6Y6Y7Y7Y8Y8Y9Y90 0 0 0
3、0 0 0 01 10 00 00 00 00 00 00 00 00 00 0 0 10 0 0 10 01 10 00 00 00 00 00 00 00 00 0 1 00 0 1 00 00 01 10 00 00 00 00 00 00 00 0 1 10 0 1 10 00 00 01 10 00 00 00 00 00 0 1 0 0 11 0 0 10 00 00 00 00 00 00 00 00 01 11 0 1 01 0 1 0d dd dd dd dd dd dd dd dd dd d d dd dd dd dd dd dd dd dd dd d1 1 1 11 1
4、1 1d dd dd dd dd dd dd dd dd dd dY0,Y1Y0,Y1需要需要4 4个输入个输入,Y2-Y7,Y2-Y7需要需要3 3个输入个输入,Y8-Y9,Y8-Y9需要需要2 2个输入个输入2 2个个4 4输入的与门，输入的与门，6 6个个3 3输入的与门，输入的与门，2 2个个2 2输入的与门输入的与门4-16译码器的设计译码器的设计,去除其中的去除其中的6个输出个输出DCBADCBAY0Y0Y1Y1Y2Y2Y3Y3Y4Y4Y5Y5Y6Y6Y7Y7Y8Y8Y9Y90 0 0 00 0 0 01 10 00 00 00 00 00 00 00 00 00 0 0 10 0
5、 0 10 01 10 00 00 00 00 00 00 00 00 0 1 00 0 1 00 00 01 10 00 00 00 00 00 00 00 0 1 10 0 1 10 00 00 01 10 00 00 00 00 00 0 1 0 0 11 0 0 10 00 00 00 00 00 00 00 00 01 11 0 1 01 0 1 00 00 00 00 00 00 00 00 00 00 0 0 00 00 00 00 00 00 00 00 00 01 1 1 11 1 1 10 00 00 00 00 00 00 00 00 00 0BADC00 01 11 1
6、00001111001234567891010个个4 4输入的与门输入的与门6.41 专用译码器的设计专用译码器的设计输入：输入：A2、A1、A0，使能信号使能信号CS_L输出：输出：8个信号个信号6.43SSI器件：器件：P.361 图图6-186.51 16-4编码器编码器1 0 0 0 0 0 0 0 1 1 1 10 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 00 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 10 0 0 0 0 0 0 1 0 0 0 0I15 I14 I8 I7 I1 I0Y3
7、 Y2 Y1 Y0Y3=I15+I14+Y3=I15+I14+I8+I8 Y2=I15+I14+I13+I12+I7+I6+I5+I4Y2=I15+I14+I13+I12+I7+I6+I5+I4Y1=I15+I14+I11+I10+I7+I6+I3+I2Y1=I15+I14+I11+I10+I7+I6+I3+I2 Y0=I15+I13+Y0=I15+I13+I1+I1用与非门实现用与非门实现: :Y3=I15_L+I14_L+I8_LY2=I15_L+I14_L+I13_L+ I12_L+ I7_L+I6_L+ I5_L+I4_LY1=I15_L+I14_L+I11_L+ I10L+I7_L+I6_L+ I3_L+I2_LY0=I15_L+I13_L+I1_L6.63 设计设计3输入输入5位的多路复用器（位的多路复用器（24引脚）引脚）输入、输出端口数分配输入、输出端口数分配D0: 1D05D0D1: 1D15D1D2: 1D25D26.65 设计设计4输入输入18位的多路复用器位的多路复用器S2S1S0INPUT to SELECT 0 0 0A 0 0 1B 0 1 0A 0 1 1C 1 0 0A 1 0 1D 1 1 0A 1 1 1B所有的所有的C,B,AC,B,A端口都分别连到端口都分别连到S2,S1,S0S2,S1,S0
