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1、AM08X5 DatasheetAM08X5 Real-Time Clock FamilyAmbiq Micro Inc.11305 Four Points Drive, Building 2, Suite 2502014 Ambiq Micro, IAustin, TX 78726April 2014Features Ultra-low supply current (all at 3V):- 14 nA with RC oscillator- 22 nA with RC oscillator and Autocalibration- 55 nA with crystal oscillato
2、r Baseline timekeeping features:- 32.768 kHz crystal oscillator with integrated load capacitor/resistor- Counters for hundredths, seconds, minutes, hours, date, month, year, century, and week-day- Alarm capability on all counters- Programmable output clock generation (32.768 kHz to 1 year)- Countdow
3、n timer with repeat function- Automatic leap year calculation Advanced timekeeping features:- Integrated power optimized RC oscillator- Advanced crystal calibration to 2 ppm- Advanced RC calibration to 16 ppm- Automatic calibration of RC oscillator to crystal oscillator- Watchdog timer with hardware
4、 reset- Up to 256 bytes of general purpose RAM Power management features:- Automatic switchover to VBAT- External interrupt monitor- Programmable low battery detection threshold- Programmable analog voltage comparator I2C (up to 400 kHz) and 3-wire or 4-wire SPI (up to 2 MHz) serial interfaces avail
5、able Operating voltage 1.5-3.6 V Clock and RAM retention voltage 1.5-3.6 V Operating temperature 40 to 85 C All inputs include Schmitt Triggers 3x3 mm QFN-16 package Also available in wafer formApplications Smart cards Wireless sensors and tags Medical electronics Utility meters Data loggers Applian
6、ces Handsets Consumer electronics Communications equipmentDescriptionThe Ambiq Micro AM08X5 Real Time Clock family provides a groundbreaking combination of ultra-low power coupled with a highly sophisticated feature set. With power requirements significantly lower than any other industry RTC (as low
7、 as 14 nA), these are the first semiconductors based on Ambiq Micros innovative SPOTTM (Subthreshold Power Optimized Technology) CMOS platform. The AM08X5 includes on-chip oscillators to provide minimum power consumption, full RTC functions including battery backup and programmable counters and alar
8、ms for timer and watchdog functions, and either an I2C or SPI serial interface for communication with a host controller.Ambiq Micro超低功耗MCU、RTC芯片代理商：深圳擎鼎科技有限公司联系人：张小姐 邮箱：zhangkaiyunt- 电话：13802700180 QQ:249750140本公司将为您提供Demo、样品、开发资料支持，并有专业的技术工程师协助您设计应用产品。AM08X5 DatasheetDS0002V1p1Page 2 of 792014 Ambi
9、q Micro, Inc.All rights reserved.Typical Application CircuitVCCVSSFOUT/nIRQIRQVCCVSSAM08X5MCUI2C/SPIVBATSystem PowerBattery/SupercapXOXI1.5k* Total battery series impedance = 1.5k ohms, which may require an external resistorAM08X5 DatasheetDS0002V1p1Page 3 of 792014 Ambiq Micro, Inc.All rights reser
10、ved.Contents1. Family Summary . 102. Package Pins . 102.1. Pin Configuration and Connections . 102.2. Pin Descriptions . 113. Digital Architecture Summary . 134. Electrical Specifications . 144.1. Absolute Maximum Ratings . 144.2. Power Supply Parameters . 144.3. Operating Parameters . 164.4. Oscill
11、ator Parameters . 174.5. VCC Supply Current . 194.6. VBAT Supply Current . 234.7. BREF Electrical Characteristics . 264.8. IC AC Electrical Characteristics . 264.9. SPI AC Electrical Characteristics . 274.10. Power On AC Electrical Characteristics . 295. Functional Description . 305.1. IC Interface
12、. 315.1.1. Bus Not Busy . 315.1.2. Start Data Transfer . 325.1.3. Stop Data Transfer . 325.1.4. Data Valid . 325.1.5. Acknowledge . 325.1.6. Offset Address Transmission . 335.1.7. Write Operation . 335.1.8. Read Operation . 335.2. SPI Interface . 345.2.1. Write Operation . 345.2.2. Read Operation .
13、345.3. XT Oscillator . 355.4. RC Oscillator . 355.5. RTC Counter Access . 355.6. Hundredths Synchronization . 355.7. Generating Hundredths of a Second . 365.8. Watchdog Timer . 365.9. Digital Calibration . 365.9.1. XT Oscillator Digital Calibration . 365.9.2. RC Oscillator Digital Calibration . 375.
14、10. Autocalibration . 385.10.1. Autocalibration Operation . 385.10.2. XT Autocalibration Mode . 385.10.3. RC Autocalibration Mode . 395.10.4. Autocalibration Frequency and Control . 395.10.5. Autocalibration Filter (AF) Pin . 395.10.6. Autocalibration Fail . 395.11. Oscillator Failure Detection . 40
15、5.12. Interrupts . 405.12.1. Interrupt Summary . 405.12.2. Alarm Interrupt AIRQ . 41AM08X5 DatasheetDS0002V1p1Page 4 of 792014 Ambiq Micro, Inc.All rights reserved.5.12.3. Countdown Timer Interrupt TIRQ . 415.12.4. Watchdog Timer Interrupt WIRQ . 415.12.5. Battery Low Interrupt BLIRQ . 415.12.6. Ext
16、ernal Interrupts X1IRQ and X2IRQ . 415.12.7. Oscillator Fail Interrupt OFIRQ . 425.12.8. Autocalibration Fail Interrupt ACIRQ . 425.12.9. Servicing Interrupts . 425.13. Power Control and Switching . 425.13.1. Battery Low Flag and Interrupt . 435.13.2. Analog Comparator . 445.13.3. Pin Control and Le
17、akage Management . 445.13.4. Power Up Timing . 445.14. Software Reset . 455.15. Trickle Charger . 456. Registers . 466.1. Register Definitions and Memory Map . 466.2. Time and Date Registers . 486.2.1. 0x00 - Hundredths . 486.2.2. 0x01 - Seconds . 486.2.3. 0x02 - Minutes . 496.2.4. 0x03 - Hours . 49
18、6.2.5. 0x04 - Date . 506.2.6. 0x05 - Months . 506.2.7. 0x06 - Years . 516.2.8. 0x07 - Weekday . 516.3. Alarm Registers . 526.3.1. 0x08 - Hundredths Alarm . 526.3.2. 0x09 - Seconds Alarm . 526.3.3. 0x0A - Minutes Alarm . 536.3.4. 0x0B - Hours Alarm . 536.3.5. 0x0C - Date Alarm . 546.3.6. 0x0D - Month
19、s Alarm . 556.3.7. 0x0E - Weekday Alarm . 556.4. Configuration Registers . 566.4.1. 0x0F - Status (Read Only) . 566.4.2. 0x10 - Control1 . 576.4.3. 0x11 - Control2 . 576.4.4. 0x12 - Interrupt Mask . 586.4.5. 0x13 - SQW . 596.5. Calibration Registers . 616.5.1. 0x14 - Calibration XT . 616.5.2. 0x15 -
20、 Calibration RC Upper . 616.5.3. 0x16 - Calibration RC Lower . 626.6. Interrupt Polarity Control Register . 626.6.1. 0x17 - Interrupt Polarity Control . 626.7. Timer Registers . 636.7.1. 0x18 - Countdown Timer Control . 636.7.2. 0x19 - Countdown Timer . 656.7.3. 0x1A - Timer Initial Value . 656.7.4.
21、 0x1B - Watchdog Timer . 666.8. Oscillator Registers . 666.8.1. 0x1C - Oscillator Control . 666.8.2. 0x1D Oscillator Status Register . 67AM08X5 DatasheetDS0002V1p1Page 5 of 792014 Ambiq Micro, Inc.All rights reserved.6.9. Miscellaneous Registers . 686.9.1. 0x1F - Configuration Key . 686.10. Analog C
22、ontrol Registers . 686.10.1. 0x20 - Trickle . 686.10.2. 0x21 - BREF Control . 696.10.3. 0x26 AFCTRL . 696.10.4. 0x27 Batmode IO Register . 706.10.5. 0x2F Analog Status Register (Read Only) . 706.10.6. 0x30 Output Control Register . 716.11. ID Registers . 726.11.1. 0x28 ID0 - Part Number Upper Regist
23、er (Read Only) . 726.11.2. 0x29 ID1 - Part Number Lower Register (Read Only) . 726.11.3. 0x2A ID2 - Part Revision (Read Only) . 726.11.4. 0x2B ID3 Lot Lower (Read Only) . 736.11.5. 0x2C ID4 ID Upper (Read Only) . 736.11.6. 0x2D ID5 Unique Lower (Read Only) . 736.11.7. 0x2E ID6 Wafer (Read Only) . 74
24、6.12. Ram Registers . 746.12.1. 0x3F - Extension RAM Address . 746.12.2. 0x40 - 0x7F Standard RAM . 756.12.3. 0x80 - 0xFF Alternate RAM . 757. Package Mechanical Information . 768. Reflow Profile . 779. Ordering Information . 7810. Document Revision History . 7811. Contact Information . 7912. Legal
25、Information and Disclaimers . 79AM08X5 DatasheetDS0002V1p1Page 6 of 792014 Ambiq Micro, Inc.All rights reserved.List of FiguresFigure 1. Pin Configuration Diagram . 10Figure 2. Digital Architecture Summary . 13Figure 3. Power Supply Switchover . 14Figure 4. Calibrated RC Oscillator Typical Frequency
26、 Variation vs. Temperature . 18Figure 5. Uncalibrated RC Oscillator Typical Frequency Variation vs. Temperature . 18Figure 6. Typical VCC Current vs. Temperature in XT Mode . 20Figure 7. Typical VCC Current vs. Temperature in RC Mode . 20Figure 8. Typical VCC Current vs. Temperature in RC Autocalibr
27、ation Mode . 21Figure 9. Typical VCC Current vs. Voltage, Different Modes of Operation . 21Figure 10. Typical VCC Current vs. Voltage, IC and SPI Burst Read/Write . 22Figure 11. Typical VCC Current vs. Voltage, 32.768 kHz Clock Output . 22Figure 12. Typical VBAT Current vs. Temperature in XT Mode .
28、23Figure 13. Typical VBAT Current vs. Temperature in RC Mode . 24Figure 14. Typical VBAT Current vs. Temperature in RC Autocalibration Mode . 24Figure 15. Typical VBAT Current vs. Voltage, Different Modes of Operation . 25Figure 16. Typical VBAT Current vs. Voltage in VCC Power State . 25Figure 17.
29、IC AC Parameter Definitions . 26Figure 18. SPI AC Parameter Definitions Input . 27Figure 19. SPI AC Parameter Definitions Output . 28Figure 20. Power On AC Electrical Characteristics . 29Figure 21. Detailed Block Diagram . 30Figure 22. Basic IC Conditions . 31Figure 23. IC Acknowledge Address Operat
30、ion . 32Figure 24. IC Address Operation . 32Figure 25. IC Offset Address Transmission . 33Figure 26. IC Write Operation . 33Figure 27. IC Read Operation . 33Figure 28. SPI Write Operation . 34Figure 29. SPI Read Operation . 35Figure 30. Power States . 43Figure 31. Power Up Timing . 45Figure 32. Tric
31、kle Charger . 45Figure 33. Package Mechanical Diagram . 76Figure 34. Reflow Soldering Diagram . 77AM08X5 DatasheetDS0002V1p1Page 7 of 792014 Ambiq Micro, Inc.All rights reserved.List of TablesTable 1: Family Summary . 10Table 2: Pin Connections . 10Table 3: Pin Descriptions . 11Table 4: Absolute Max
32、imum Ratings . 14Table 5: Power Supply and Switchover Parameters . 15Table 6: Operating Parameters . 16Table 7: Oscillator Parameters . 17Table 8: VCC Supply Current . 19Table 9: VBAT Supply Current . 23Table 10: BREF Parameters . 26Table 11: IC AC Electrical Parameters . 27Table 12: SPI AC Electric
33、al Parameters . 28Table 13: Power On AC Electrical Parameters . 29Table 14: Autocalibration Modes . 39Table 15: Interrupt Summary . 41Table 16: Register Definitions (0x00 to 0x0F) . 46Table 17: Register Definitions (0x10 to 0xFF) . 47Table 18: Hundredths Register . 48Table 19: Hundredths Register Bi
34、ts . 48Table 20: Seconds Register . 48Table 21: Seconds Register Bits . 48Table 22: Minutes Register . 49Table 23: Minutes Register Bits . 49Table 24: Hours Register (12 Hour Mode) . 49Table 25: Hours Register Bits (12 Hour Mode) . 49Table 26: Hours Register (24 Hour Mode) . 50Table 27: Hours Regist
35、er Bits (24 Hour Mode) . 50Table 28: Date Register . 50Table 29: Date Register Bits . 50Table 30: Months Register . 50Table 31: Months Register Bits . 51Table 32: Years Register . 51Table 33: Years Register Bits . 51Table 34: Weekdays Register . 51Table 35: Weekdays Register Bits . 52Table 36: Hundr
36、edths Alarm Register . 52Table 37: Hundredths Alarm Register Bits . 52Table 38: Seconds Alarm Register . 52Table 39: Seconds Alarm Register Bits . 53Table 40: Minutes Alarm Register . 53Table 41: Minutes Alarm Register Bits . 53Table 42: Hours Alarm Register (12 Hour Mode) . 53Table 43: Hours Alarm
37、Register Bits (12 Hour Mode) . 54Table 44: Hours Alarm Register (24 Hour Mode) . 54Table 45: Hours Alarm Register Bits (24 Hour Mode) . 54Table 46: Date Alarm Register . 54Table 47: Date Alarm Register Bits . 55Table 48: Months Alarm Register . 55Table 49: Months Alarm Register Bits . 55Table 50: We
38、ekdays Alarm Register . 55Table 51: Weekdays Alarm Register Bits . 56Table 52: Status Register . 56AM08X5 DatasheetDS0002V1p1Page 8 of 792014 Ambiq Micro, Inc.All rights reserved.Table 53: Status Register Bits . 56Table 54: Control1 Register . 57Table 55: Control1 Register Bits . 57Table 56: Control
39、2 Register . 57Table 57: Control2 Register Bits . 57Table 58: nIRQ2 Pin Control . 58Table 59: FOUT/nIRQ Pin Control . 58Table 60: Interrupt Mask Register . 58Table 61: Interrupt Mask Register Bits . 58Table 62: SQW Register . 59Table 63: SQW Register Bits . 59Table 64: Square Wave Function Select .
40、60Table 65: Calibration XT Register . 61Table 66: Calibration XT Register Bits . 61Table 67: Calibration RC Upper Register . 61Table 68: Calibration RC Upper Register Bits . 61Table 69: CMDR Function . 61Table 70: Calibration RC Lower Register . 62Table 71: Calibration RC Lower Register Bits . 62Tab
41、le 72: Interrupt Polarity Control Register . 62Table 73: Interrupt Polarity Control Register Bits . 62Table 74: Countdown Timer Control Register . 63Table 75: Countdown Timer Control Register Bits . 63Table 76: Repeat Function . 63Table 77: Countdown Timer Function Select . 64Table 78: Countdown Tim
42、er Register . 65Table 79: Countdown Timer Register Bits . 65Table 80: Timer Initial Value Register . 65Table 81: Timer Initial Value Register Bits . 65Table 82: Watchdog Timer Register . 66Table 83: Watchdog Timer Register Bits . 66Table 84: Watchdog Timer Frequency Select . 66Table 85: Oscillator C
43、ontrol Register . 66Table 86: Oscillator Control Register Bits . 67Table 87: Oscillator Status Register . 67Table 88: Oscillator Status Register Bits . 67Table 89: Configuration Key Register . 68Table 90: Configuration Key Register Bits . 68Table 91: Trickle Register . 68Table 92: Trickle Register B
44、its . 68Table 93: Trickle Charge Output Resistor . 69Table 94: BREF Control Register . 69Table 95: BREF Control Register Bits . 69Table 96: VBAT Reference Voltage . 69Table 97: AFCTRL Register . 70Table 98: AFCTRL Register Bits . 70Table 99: Batmode IO Register . 70Table 100: Batmode IO Register Bit
45、s . 70Table 101: Analog Status Register . 70Table 102: Analog Status Register Bits . 71Table 103: Output Control Register . 71Table 104: Output Control Register Bits . 71Table 105: 28 ID0 Part Number Upper Register . 72Table 106: 28 ID1 Part Number Lower Register . 72AM08X5 DatasheetDS0002V1p1Page 9
46、 of 792014 Ambiq Micro, Inc.All rights reserved.Table 107: 2A ID2 Part Revision Register . 72Table 108: 2A ID2 Part Revision Register Bits . 72Table 109: 2B ID3 Lot Lower Register . 73Table 110: 2B ID3 Lot Lower Register Bits . 73Table 111: 2C ID4 ID Upper Register . 73Table 112: 2C ID4 ID Upper Reg
47、ister Bits . 73Table 113: 2D ID5 ID Lower Register . 73Table 114: 2D ID5 ID Lower Register Bits . 74Table 115: 2E ID6 Wafer Register . 74Table 116: 2E ID6 Wafer Register Bits . 74Table 117: 3F Extension RAM Address Register . 74Table 118: 3F Extension RAM Address Register Bits . 74Table 119: Reflow
48、Soldering Requirements . 77Table 120: Ordering Information . 78Table 121: Document Revision History . 78AM08X5 DatasheetDS0002V1p1Page 10 of 792014 Ambiq Micro, Inc.All rights reserved.1.Family SummaryThe AM08X5 family consists of several members (see Table 1). All devices are supplied in a standard
49、 3x3 mm QFN-16 package. Members of the software and pin compatible AM18X5 RTC with Power Management family are also listed. 2.Package Pins2.1Pin Configuration and ConnectionsFigure 1 and Table 2 show the QFN-16 pin configurations for the AM08X5 parts. Pins labeled NC must be left unconnected. The th
50、ermal pad, pin 17, on the QFN-16 packages must be connected to VSS.Figure 1. Pin Configuration DiagramTable 1: Family SummaryPart #Baseline TimekeepingAdvanced TimekeepingPower ManagementInterfaceXT OscNumber of GP OutputsRC OscCalib/Auto-calibWatch-dogRAM (B)VBATSwitchReset Mgmt Ext IntPower Switch
51、 and Sleep FSMAM08054256I2CAM08153256SPISoftware and Pin Compatible AM18X5 Family ComponentsAM18054256I2CAM18153256SPITable 2: Pin ConnectionsPin NamePin TypeFunctionPin NumberAM0805AM0815VSSPowerGround9,1717VCCPowerSystem power supply1313XIXTCrystal input1616NCWDINCnIRQ2FOUT/nIRQEXTIVSSSCLSDAVBATXO
52、XIVCCnTIRQ1NCWDINCnIRQ2FOUT/nIRQEXTISDIXOXIVCCnCE1SCLSDOVBATAM0805AM0815CLKOUT/nIRQ3CLKOUT/nIRQ3AFAFVSSPADVSSPADAM08X5 DatasheetDS0002V1p1Page 11 of 792014 Ambiq Micro, Inc.All rights reserved.2.2Pin DescriptionsTable 3 provides a description of the pin connections.XOXTCrystal output1515AFOutputAuto
53、calibration filter1414VBATPowerBattery power supply55SCLInputI2C or SPI interface clock77SDOOutputSPI data output6SDIInputSPI data input9nCEInputSPI chip select12SDAInputI2C data input/output6EXTIInputExternal interrupt input1010WDIInputWatchdog reset input22FOUT/nIRQOutputInt 1/function output1111n
54、IRQ2OutputInt 2 output44CLKOUT/nIRQ3OutputInt 3/clock output88nTIRQOutputTimer interrupt output12Table 3: Pin DescriptionsPin NameDescriptionVSSGround connection. In the QFN-16 packages the ground slug on the bottom of the package must be connected to VSS.VCCPrimary power connection. If a single pow
55、er supply is used, it must be connected to VCC.VBATBattery backup power connection. If a backup battery is not present, VBAT is normally left floating or grounded, but it may also be used to provide the analog input to the internal comparator (see Analog-Comparator).XICrystal oscillator input connec
56、tion.XOCrystal oscillator output connection.AFAutocalibration filter connection. A 47pF ceramic capacitor should be placed between this pin and VSS for improved Autocalibration mode timing accuracy.SCLI/O interface clock connection. It provides the SCL input in both I2C and SPI interface parts.SDA (
57、only available in I2C environments)I/O interface I2C data connection. SDO (only available in SPI environments)I/O interface SPI data output connection. SDII/O interface SPI data input connection. nCE (only available in SPI environments)I/O interface SPI chip select input connection. It is an active
58、low signal. A pull-up resistor is recom-mended to be connected to this pin to ensure it is not floating. A pull-up resistor also prevents inadver-tent writes to the RTC during power transitions.Table 2: Pin ConnectionsPin NamePin TypeFunctionPin NumberAM0805AM0815AM08X5 DatasheetDS0002V1p1Page 12 of
59、 792014 Ambiq Micro, Inc.All rights reserved.EXTIExternal interrupt input connection. It may be used to generate an External 1 interrupt with polarity selected by the EX1P bit if enabled by the EX1E bit. The value of the EXTI pin may be read in the EXIN register bit. This pin does not have an intern
60、al pull resistor. It must not be left floating or the RTC may consume higher current.WDIWatchdog Timer reset input connection. It may also be used to generate an External 2 interrupt with polarity selected by the EX2P bit if enabled by the EX2E bit. The value of the WDI pin may be read in the WDIN r
61、egister bit. This pin does not have an internal pull resistor. It must not be left floating or the RTC may consume higher current.FOUT/nIRQPrimary interrupt output connection. FOUT/nIRQ may be configured to generate several signals as a function of the OUT1S field (see 0x11 - Control2). FOUT/nIRQ is
62、 also asserted low on a power up until the AM08X5 has exited the reset state and is accessible via the I/O interface.1.FOUT/nIRQ can drive the value of the OUT bit.2.FOUT/nIRQ can drive the inverse of the combined interrupt signal IRQ (see Interrupts).3.FOUT/nIRQ can drive the square wave output (se
63、e 0x13 - SQW) if enabled by SQWE.4.FOUT/nIRQ can drive the inverse of the alarm interrupt signal AIRQ (see Interrupts).nIRQ21.Secondary interrupt output connection. It is an open drain output. nIRQ2 may be configured to generate several signals as a function of the OUT2S field (see 0x11 - Control2).
64、nIRQ2 can drive the value of the OUTB bit.2.nIRQ2 can drive the square wave output (see 0x13 - SQW) if enabled by SQWE.3.nIRQ2 can drive the inverse of the combined interrupt signal IRQ (see Interrupts).4.nIRQ2 can drive the inverse of the alarm interrupt signal AIRQ (see Interrupts).5.nIRQ2 can dri
65、ve either sense of the timer interrupt signal TIRQ.nTIRQ (only available in I2C environments)Timer interrupt output connection. It is an open drain output. nTIRQ always drives the active low nTIRQ signal.CLKOUT/nIRQ3Square Wave output connection. It is a push-pull output, and may be configured to ge
66、nerate one of two signals.1.CLKOUT/nIRQ3 can drive the value of the OUT bit.2.CLKOUT/nIRQ3 can drive the square wave output (see 0x13 - SQW) if enabled by SQWE.Table 3: Pin DescriptionsPin NameDescriptionAM08X5 DatasheetDS0002V1p1Page 13 of 792014 Ambiq Micro, Inc.All rights reserved.3.Digital Archi
67、tecture SummaryFigure 2 illustrates the overall architecture of the pin inputs and outputs of the AM08X5.Figure 2. Digital Architecture SummaryCDTnTIRQTIRQAlarmsSQWMuxCalendarCountersOUTCLKOUT/nIRQ3OUT1MuxAIRQFOUT/nIRQIRQOR+MskOUT2MuxEXTIWDIOUTBIRQWDTOFACFBLnIRQ2PowerOnSQWAM08X5 DatasheetDS0002V1p1P
68、age 14 of 792014 Ambiq Micro, Inc.All rights reserved.4.Electrical Specifications4.1Absolute Maximum RatingsTable 4 lists the absolute maximum ratings.4.2Power Supply ParametersFigure 3 and Table 5 describe the power supply and switchover parameters. See Power Control and Switching for a detailed de
69、scription of the operations.Figure 3. Power Supply SwitchoverTable 4: Absolute Maximum RatingsSYMBOLPARAMETERTEST CONDITIONSMINTYPMAXUNITVCCSystem Power Voltage-0.33.8VVBATBattery Voltage-0.33.8VVIInput voltageVCC Power state-0.3VCC+ 0.3VVIInput voltageVBAT Power state-0.3VBAT+ 0.3VVOOutput voltageV
70、CC Power state-0.3VCC+ 0.3VVOOutput voltageVBAT Power state-0.3VBAT+ 0.3VIIInput current-1010mAIOOutput current-2020mAVESDESD VoltageCDM500VHBM4000VILULatch-up Current100mATSTGStorage Temperature-55125CTOPOperating Temperature-4085CTSLDLead temperatureHand soldering for 10 seconds300CTREFReflow sold
71、ering temperatureReflow profile per JEDEC J-STD-020D260CVCCVBATPower StatePORVCCSTVCCRSTVCCPowerVCCSTPORVCCSWFVCCPowerVBATPowerVBATSWVCCSWRVCCPowerVCCSWFVBATRSTVBATPowerPORAM08X5 DatasheetDS0002V1p1Page 15 of 792014 Ambiq Micro, Inc.All rights reserved.For Table 5, TA = -40 C to 85 C, TYP values at
72、25 C.Table 5: Power Supply and Switchover ParametersSYMBOLPARAMETERPWRTYPEPOWER STATETEST CONDITIONSMINTYPMAXUNITVCCSystem Power VoltageVCCStaticVCC PowerClocks operating and RAM andregisters retained1.5 3.6VVCCIOVCC I/O Interface VoltageVCCStaticVCC PowerI2C or SPI opera-tion1.5 3.6VVCCSTVCC Start-
73、up Voltage(1)VCCRisingPOR - VCC Power 1.6 VVCCRSTVCC Reset VoltageVCCFallingVCC Power - PORVBAT VCC PowerVBAT VBATRST1.61.7VVCCSWFVCC Falling Switch-over Threshold VoltageVCCFallingVCC Power - VBAT PowerVBAT VBATSW,MIN1.21.5VVCCSWHVCC Switchover Thresh-old Hysteresis(2)VCCHyst.VCC Power VBAT Power 7
74、0 mVVCCFSVCC Falling Slew Rate to switch to VBAT state(4)VCCFallingVCC Power - VBAT PowerVCC VBAT Power 1.6 3.6VVBATRSTFalling Battery POR Volt-age(7)VBATFallingVBAT Power - PORVCC VCCSWF1.11.4VVBMRGVBAT Margin above VCC(3)VBATStaticVBAT Power 200 mVVBATESRVBAT supply series resis-tance(6)VBATStatic
75、VBAT Power1.01.5k(1)VCC must be above VCCST to exit the POR state, independent of the VBAT voltage.(2)Difference between VCCSWR and VCCSWF.(3)VBAT must be higher than VCC by at least this voltage to ensure the AM08X5 remains in the VBAT Power state.(4)Maximum VCC falling slew rate to guarantee corre
76、ct switchover to VBAT Power state. There is no VCC falling slew rate requirement if switching to the VBAT power source is not required.(5)VBAT voltage to guarantee correct transition to VBAT Power state when VCC falls.(6)Total series resistance of the power source attached to the VBAT pin. The optim
77、al value is 1.5k, which may require an external resistor. VBAT power source ESR + external resistor value = 1.5k(7)VBATRST is also the static voltage required on VBAT for register data retention.AM08X5 DatasheetDS0002V1p1Page 16 of 792014 Ambiq Micro, Inc.All rights reserved.4.3Operating ParametersT
78、able 6 lists the operating parameters. For Table 6, TA = -40 C to 85 C, TYP values at 25 C.Table 6: Operating ParametersSYMBOLPARAMETERTEST CONDITIONSVCCMINTYPMAXUNITVT+Positive-going Input Thresh-old Voltage3.0V1.52.0V1.8V1.11.25VT-Negative-going Input Thresh-old Voltage3.0V0.80.9V1.8V0.50.6IILEAKI
79、nput leakage current3.0V0.0280nACIInput capacitance3pFVOHHigh level output voltage on push-pull outputs1.7V 3.6V0.8VCCVVOLLow level output voltage1.7V 3.6V0.2VCCVIOHHigh level output current on push-pull outputsVOH = 0.8VCC1.7V-2-3.8mA1.8V-3-4.33.0V-7-113.6V-8.8-15IOLLow level output currentVOL = 0.
80、2VCC1.7V3.35.9mA1.8V6.16.93.0V17193.6V1820IOLEAKOutput leakage current0.0280nAAM08X5 DatasheetDS0002V1p1Page 17 of 792014 Ambiq Micro, Inc.All rights reserved.4.4Oscillator ParametersTable 7 lists the oscillator parameters.For Table 7, TA = -40 C to 85 C unless otherwise indicated.VCC = 1.7 to 3.6V,
81、 TYP values at 25 C and 3.0V.Table 7: Oscillator ParametersSYMBOLPARAMETERTEST CONDITIONSMINTYPMAXUNITFXTXI and XO pin Crystal Fre-quency32.768kHzFOFXT Oscillator failure detection frequency8kHzCINXInternal XI and XO pin capac-itance1pFCEXExternal XI and XO pin PCB capacitance1pFOAXTXT Oscillation A
82、llowanceAt 25C using a 32.768 kHz crystal270320kFRCCCalibrated RC Oscillator Fre-quency(1)Factory Calibrated at 25C, VCC = 2.8V128HzFRCUUncalibrated RC Oscillator FrequencyCalibration Disabled (OFF-SETR = 0)89122220HzJRCCCRC Oscillator cycle-to-cycle jitterCalibration Disabled (OFF-SETR = 0) 128 Hz2
83、000ppmCalibration Disabled (OFF-SETR = 0) 1 Hz500AXTXT mode digital calibration accuracy(1)Calibrated at an initial tem-perature and voltage-22ppmAACAutocalibration mode timing accuracy, 512 second period, TA = -10C to 60C(1)24 hour run time35ppm1 week run time201 month run time101 year run time3TAC
84、Autocalibration mode operat-ing temperature(2)-1060C(1)Timing accuracy is specified at 25C after digital calibration of the internal RC oscillator and 32.768 kHz crystal. A typical 32.768 kHz tuning fork crystal has a negative temperature coefficient with a parabolic frequency deviation, which can r
85、esult in a change of up to 150 ppm across the entire operating temperature range of -40C to 85C in XT mode. Autocal-ibration mode timing accuracy is specified relative to XT mode timing accuracy from -10C to 60C.(2)Outside of this temperature range, the RC oscillator frequency change due to temperat
86、ure may be outside of the allowable RC digital calibration range (+/-12%) for autocalibration mode. When this happens, an autocalibration failure will occur and the ACF interrupt flag is set. The AM08X5 should be switched to use the XT oscillator as its clock source when this occurs. Please see the
87、Autocalibration Fail section for more details.AM08X5 DatasheetDS0002V1p1Page 18 of 792014 Ambiq Micro, Inc.All rights reserved.Figure 4 shows the typical calibrated RC oscillator frequency variation vs. temperature. RC oscillator calibrated at 2.8V, 25C.Figure 4. Calibrated RC Oscillator Typical Fre
88、quency Variation vs. TemperatureFigure 5 shows the typical uncalibrated RC oscillator frequency variation vs. temperature.Figure 5. Uncalibrated RC Oscillator Typical Frequency Variation vs. Temperature1151201251301351401451504030201001020304050607080RCFrequency(Hz)Temperature(C)VCC=1.8VVCC=3.0VTA=2
89、5 C1151201251301351401454030201001020304050607080RCFrequency(Hz)Temperature(C)VCC=1.8VVCC=3.0VTA=25 CAM08X5 DatasheetDS0002V1p1Page 19 of 792014 Ambiq Micro, Inc.All rights reserved.4.5VCC Supply CurrentTable 8 lists the current supplied into the VCC power input under various conditions.For Table 8,
90、 TA = -40 C to 85 C, VBAT = 0 V to 3.6 VTYP values at 25 C, MAX values at 85 C, VCC Power stateTable 8: VCC Supply CurrentSYMBOLPARAMETERTEST CONDITIONSVCCMINTYPMAXUNITIVCC:I2CVCC supply current during I2C burst read/write400kHz bus speed, 2.2k pull-up resistors on SCL/SDA(1)3.0V610A1.8V1.53IVCC:SPI
91、WVCC supply current during SPI burst write2 MHz bus speed (2)3.0V812A1.8V46IVCC:SPIRVCC supply current during SPI burst read2 MHz bus speed (2)3.0V2337A1.8V1321IVCC:XTVCC supply current in XT oscil-lator modeTime keeping mode with XT oscillator running(3)3.0V55330nA1.8V51290IVCC:RCVCC supply current
92、 in RC oscil-lator modeTime keeping mode with only the RC oscillator running (XT oscillator is off)(3)3.0V14220nA1.8V11170IVCC:ACALAverage VCC supply current in Autocalibrated RC oscillator modeTime keeping mode with only RC oscillator running and Auto-calibration enabled. ACP = 512 seconds(3)3.0V22
93、235nA1.8V18190IVCC:CK32Additional VCC supply current with CLKOUT at 32.786 kHzTime keeping mode with XT oscillator running, 32.786 kHz square wave on CLKOUT(4)3.0V3.68A1.8V2.25IVCC:CK128Additional VCC supply current with CLKOUT at 128 HzAll time keeping modes, 128 Hz square wave on CLKOUT(4)3.0V735n
94、A1.8V2.520(1)Excluding external peripherals and pull-up resistor current. All other inputs (besides SDA and SCL) are at 0V or VCC. AM0805 only. Test conditions: Continuous burst read/write, 0x55 data pattern, 25 s between each data byte, 20 pF load on each bus pin.(2)Excluding external peripheral cu
95、rrent. All other inputs (besides SDI, nCE and SCL) are at 0V or VCC. AM0815 only. Test conditions: Continuous burst write, 0x55 data pattern, 25 s between each data byte, 20 pF load on each bus pin.(3)All inputs and outputs are at 0 V or VCC.(4)All inputs and outputs except CLKOUT are at 0 V or VCC.
96、 15 pF capacitive load on CLKOUT.AM08X5 DatasheetDS0002V1p1Page 20 of 792014 Ambiq Micro, Inc.All rights reserved.Figure 6 shows the typical VCC power state operating current vs. temperature in XT mode.Figure 6. Typical VCC Current vs. Temperature in XT ModeFigure 7 shows the typical VCC power state
97、 operating current vs. temperature in RC mode.Figure 7. Typical VCC Current vs. Temperature in RC Mode4050607080901001101201304030201001020304050607080VCCPowerState,XTModeCurrent(nA)Temperature(C)VCC=1.8VVCC =3.0VTA=25C5152535455565754030201001020304050607080VCCPowerState,RCModeCurrent(nA)Temperatur
98、e(C)VCC=1.8VVCC=3.0VTA=25CAM08X5 DatasheetDS0002V1p1Page 21 of 792014 Ambiq Micro, Inc.All rights reserved.Figure 8 shows the typical VCC power state operating current vs. temperature in RC Autocalibration mode.Figure 8. Typical VCC Current vs. Temperature in RC Autocalibration ModeFigure 9 shows th
99、e typical VCC power state operating current vs. voltage for XT Oscillator and RC Oscillator modes and the average current in RC Autocalibrated mode.Figure 9. Typical VCC Current vs. Voltage, Different Modes of Operation51015202530354045505540302010010203040506070VCCPowerState,AutocalModeCurrent(nA)T
100、emperature(C)VCC=1.8VVCC=3.0VTA=25C0102030405060701.522.533.5VCCPowerState Current(nA)VCCVoltage(V)RCOscillator ModeXTOscillator ModeRCAutocalibratedModeTA=25CAM08X5 DatasheetDS0002V1p1Page 22 of 792014 Ambiq Micro, Inc.All rights reserved.Figure 10 shows the typical VCC power state operating curren
101、t during continuous I2C and SPI burst read and write activity. Test conditions: TA = 25 C, 0x55 data pattern, 25 s between each data byte, 20 pF load on each bus pin, pull-up resistor current not included.Figure 10. Typical VCC Current vs. Voltage, IC and SPI Burst Read/WriteFigure 11 shows the typi
102、cal VCC power state operating current with a 32.768 kHz clock output on the CLKOUT pin. Test conditions: TA = 25 C, All inputs and outputs except CLKOUT are at 0 V or VCC. 15 pF capacitive load on the CLKOUT pin.Figure 11. Typical VCC Current vs. Voltage, 32.768 kHz Clock Output0510152025301.822.22.
103、42.62.833.23.43.6VCCCurrent(A)VCCVoltage(V)I2C BurstRead/WriteSPI BurstReadSPIBurst WriteTA=25C0123451.822.22.42.62.833.23.43.6VCCCurrent(A)VCCVoltage(V)TA=25 CAM08X5 DatasheetDS0002V1p1Page 23 of 792014 Ambiq Micro, Inc.All rights reserved.4.6VBAT Supply CurrentTable 9 lists the current supplied in
104、to the VBAT power input under various conditions.Figure 12 shows the typical VBAT power state operating current vs. temperature in XT mode.Figure 12. Typical VBAT Current vs. Temperature in XT ModeFor Table 9, TA = -40 C to 85 C, TYP values at 25 C, MAX values at 85 C, VBAT Power state.Table 9: VBAT
105、 Supply CurrentSYMBOLPARAMETERTEST CONDITIONSVCCVBATMINTYPMAXUNITIVBAT:XTVBAT supply current in XT oscillator modeTime keeping mode with XT oscillator running(1) VCCSWF3.0V56330nA1.8V52290IVBAT:RCVBAT supply current in RC oscillator modeTime keeping mode with only the RC oscillator run-ning (XT osci
106、llator is off)(1) VCCSWF3.0V16220nA1.8V12170IVBAT:ACALAverage VBAT supply current in Autocalibrated RC oscillator modeTime keeping mode with the RC oscillator running. Autocalibration enabled. ACP = 512 seconds(1) VCCSWF3.0V24235nA1.8V20190IVBAT:VCCVBAT supply current in VCC powered modeVCC powered
107、mode(1)1.7 - 3.6 V3.0V-50.620nA1.8V-100.516(1)Test conditions: All inputs and outputs are at 0 V or VCC.4050607080901001101201304030201001020304050607080VBATPowerState,XTModeCurrent(nA)Temperature(C)VBAT=1.8VVBAT=3.0VTA=25 CAM08X5 DatasheetDS0002V1p1Page 24 of 792014 Ambiq Micro, Inc.All rights rese
108、rved.Figure 13 shows the typical VBAT power state operating current vs. temperature in RC mode.Figure 13. Typical VBAT Current vs. Temperature in RC ModeFigure 14 shows the typical VBAT power state operating current vs. temperature in RC Autocalibration mode.Figure 14. Typical VBAT Current vs. Tempe
109、rature in RC Autocalibration Mode5152535455565754030201001020304050607080VBATPowerState,RCModeCurrent(nA)Temperature(C)VBAT=1.8VVBAT=3.0VTA=25 C51015202530354045505540302010010203040506070VBATPowerState,AutocalModeCurrent(nA)Temperature(C)VBAT=1.8VVBAT=3.0VTA=25 CAM08X5 DatasheetDS0002V1p1Page 25 of
110、 792014 Ambiq Micro, Inc.All rights reserved.Figure 15 shows the typical VBAT power state operating current vs. voltage for XT Oscillator and RC Oscillator modes and the average current in RC Autocalibrated mode, VCC = 0 V.Figure 15. Typical VBAT Current vs. Voltage, Different Modes of OperationFigu
111、re 16 shows the typical VBAT current when operating in the VCC power state, VCC = 1.7 V.Figure 16. Typical VBAT Current vs. Voltage in VCC Power State0102030405060701.522.533.5VBATCurrent(nA)VBATVoltage(V)RCOscillator ModeXTOscillator ModeRCAutocalibratedModeTA=25 C00.10.20.30.40.50.60.70.80.91.522.
112、533.5VBATCurrent(nA)VBATVoltage(V)TA=25 C, VCC =1.7VAM08X5 DatasheetDS0002V1p1Page 26 of 792014 Ambiq Micro, Inc.All rights reserved.4.7BREF Electrical CharacteristicsTable 10 lists the parameters of the VBAT voltage thresholds. BREF values other than those listed in the table are not supported.4.8I
113、C AC Electrical CharacteristicsFigure 17 and Table 11 describe the I2C AC electrical parameters.Figure 17. IC AC Parameter DefinitionsFor Table 10, TA = -20 C to 70 C, TYP values at 25 C, VCC = 1.7 to 3.6V.Table 10: BREF ParametersSYMBOLPARAMETERBREFMINTYPMAXUNITVBRFVBAT falling threshold01112.32.53
114、.3V10111.92.12.811011.61.82.511111.4VBRRVBAT rising threshold01112.63.03.4V10112.12.52.911011.92.22.711111.6VBRHVBAT threshold hysteresis01110.5V10110.411010.411110.2TBRVBAT analog comparator recom-mended operating temperature rangeAll values-2070CtBUFSCLSDAtHD:STAtLOWtRISESDAtSU:STAtHD:DATtHIGHtSU:
115、DATtSU:STOtFALLAM08X5 DatasheetDS0002V1p1Page 27 of 792014 Ambiq Micro, Inc.All rights reserved.4.9SPI AC Electrical CharacteristicsFigure 18, Figure 19, and Table 12 describe the SPI AC electrical parameters.Figure 18. SPI AC Parameter Definitions InputFor Table 11, TA = -40 C to 85 C, TYP values a
116、t 25 C.Table 11: IC AC Electrical ParametersSYMBOLPARAMETERVCCMINTYPMAXUNITfSCLSCL input clock frequency1.7V-3.6V10400kHztLOWLow period of SCL clock1.7V-3.6V1.3stHIGHHigh period of SCL clock1.7V-3.6V600nstRISERise time of SDA and SCL1.7V-3.6V300nstFALLFall time of SDA and SCL1.7V-3.6V300nstHD:STASTA
117、RT condition hold time1.7V-3.6V600nstSU:STASTART condition setup time1.7V-3.6V600nstSU:DATSDA setup time1.7V-3.6V100nstHD:DATSDA hold time1.7V-3.6V0nstSU:STOSTOP condition setup time1.7V-3.6V600nstBUFBus free time before a new transmission1.7V-3.6V1.3sSCLtHIGHtLOWnCEtSU:NCESDItSU:SDItHD:SDIMSB INLSB
118、 INtRISEtFALLtHD:NCEtSU:CEtBUFAM08X5 DatasheetDS0002V1p1Page 28 of 792014 Ambiq Micro, Inc.All rights reserved.Figure 19. SPI AC Parameter Definitions OutputFor Table 12, TA = -40 C to 85 C, TYP values at 25 C.Table 12: SPI AC Electrical ParametersSYMBOLPARAMETERVCCMINTYPMAXUNITfSCLSCL input clock f
119、requency1.7V3.6V0.012MHztLOWLow period of SCL clock1.7V3.6V200nstHIGHHigh period of SCL clock1.7V3.6V200nstRISERise time of all signals1.7V3.6V1stFALLFall time of all signals1.7V3.6V1stSU:NCEnCE low setup time to SCL1.7V3.6V200nstHD:NCEnCE hold time to SCL1.7V3.6V200nstSU:CEnCE high setup time to SC
120、L1.7V3.6V200nstSU:SDISDI setup time1.7V3.6V40nstHD:SDISDI hold time1.7V3.6V50nstSU:SDOSDO output delay from SCL1.7V3.6V150nstHD:SDOSDO output hold from SCL1.7V3.6V0nstHZSDO output Hi-Z from nCE1.7V3.6V250nstBUFnCE high time before a new transmission1.7V3.6V200nsSCLnCESDItHD:SDOtSU:SDOSDOADDR LSBMSB
121、OUTLSB OUTtHZAM08X5 DatasheetDS0002V1p1Page 29 of 792014 Ambiq Micro, Inc.All rights reserved.4.10 Power On AC Electrical CharacteristicsFigure 20 and Table 13 describe the power on AC electrical characteristics for the FOUT pin and XT oscillator.Figure 20. Power On AC Electrical CharacteristicsFor
122、Table 13, TA = -40 C to 85 C, VBAT 1.2 VTable 13: Power On AC Electrical ParametersSYMBOLPARAMETERVCCTAMINTYPMAXUNITtLOW:VCCLow period of VCC to ensure a valid POR1.7V3.6V85 C0.1s25 C0.1-20 C1.5-40 C10tVL:FOUTVCC low to FOUT low1.7V3.6V85 C0.1s25 C0.1-20 C1.5-40 C10tVH:FOUTVCC high to FOUT high1.7V3
123、.6V85 C0.4s25 C0.5-20 C3-40 C20tXTSTFOUT high to XT oscillator start1.7V3.6V85 C0.4s25 C0.4-20 C0.5-40 C1.5VCCFOUT tVL:FOUTtLOW:VCCtVH:FOUTVCCRSTVCCSTXTtXTSTAM08X5 DatasheetDS0002V1p1Page 30 of 792014 Ambiq Micro, Inc.All rights reserved.5.Functional DescriptionFigure 21 illustrates the AM08X5 funct
124、ional design.Figure 21. Detailed Block DiagramThe AM08X5 serves as a full function RTC for host processors such as microcontrollers. The AM08X5 includes 3 distinct feature groups: 1) baseline timekeeping features, 2) advanced timekeeping features, and 3) basic power management features. Functions fr
125、om each feature group may be controlled via I/O offset mapped registers. These registers are accessed using either an I2C serial interface (e.g., in the AM0805) or a SPI serial interface (e.g., in the AM0815). Each feature group is described briefly below and in greater detail in subsequent sections
126、.The baseline timekeeping feature group supports the standard 32.786 kHz crystal (XT) oscillation mode for maximum frequency accuracy with an ultra-low current draw of 55 nA. The baseline timekeeping feature group also includes a standard set of counters monitoring hundredths of a second up through
127、centuries. A complement of countdown timers and alarms may additionally be set to initiate interrupts or resets on several of the outputs.The advanced timekeeping feature group supports two additional oscillation modes: 1) RC oscillator mode, and 2) Autocalibration mode. At only 14 nA, the temperatu
128、re-compensated RC oscillator mode provides an XT OscRC OscDividerSecondsMinutesHoursDaysWeekdaysMonthsYearsPower ControlVCCVBATI2C/SPI InterfaceSCLSDA/OControlAlarmsInt/ClockFOUT/nIRQnIRQ2VSSCLKOUT/nIRQ3SDInCEWDIRAMXOXInTIRQTimerWDT100thsDividerCalibration EngineEXTIAnalogCompareAM08X5 DatasheetDS00
129、02V1p1Page 31 of 792014 Ambiq Micro, Inc.All rights reserved.even lower current draw than the XT oscillator for applications with reduced frequency accuracy requirements. A proprietary calibration algorithm allows the AM08X5 to digitally tune the RC oscillator frequency and the XT oscillator frequen
130、cy with accuracy as low as 2 ppm at a given temperature. In Autocalibration mode, the RC oscillator is used as the primary oscillation source and is periodically calibrated against the XT oscillator. Autocalibration may be done automatically every 8.5 minutes or 17 minutes and may also be initiated
131、via software. This mode enables average current draw of only 22 nA with frequency accuracy similar to the XT oscillator. The advanced timekeeping feature group also includes a rich set of input and output configuration options that enables the monitoring of external interrupts (e.g., pushbutton sign
132、als), the generation of clock outputs, and watchdog timer functionality. Power management features built into the AM08X5 enable it to operate as a backup device in both line-powered and battery-powered systems. An integrated power control module automatically detects when main power (VCC) falls belo
133、w a threshold and switches to backup power (VBAT). Up to 256B of ultra-low leakage RAM enable the storage of key parameters when operating on backup power. The AM08X5 also includes digitally-tunable voltage detection on the backup power supply.Each functional block is explained in detail in the rema
134、inder of this section. The functional descriptions refer to the registers shown in the Register Definitions (0x00 to 0x0F) and Register Definitions (0x10 to 0xFF) tables. A detailed description of all registers can be found in the Registers section of this document.5.1IC InterfaceThe AM08X5 includes
135、 a standard I2C interface. The device is accessed at addresses 0xD2/D3, and supports Fast Mode (up to 400 kHz). The I2C interface consists of two lines: one bi-directional data line (SDA) and one clock line (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pu
136、ll-up resistor. By definition, a device that sends a message is called the “transmitter”, and the device that accepts the message is called the “receiver”. The device that controls the message transfer by driving SCL is called “master”. The devices that are controlled by the master are called “slave
137、s”. The AM08X5 is always a slave device.I2C termination resistors should be above 2.2 k, and for systems with short I2C bus wires/traces and few connections these terminators can typically be as large as 22 k (for 400 kHz operation) or 56 k (for 100 kHz operation). Larger resistors will produce lowe
138、r system current consumption.The following protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as con
139、trol signals.A number of bus conditions have been defined (see Figure 22) and are described in the following sections.Figure 22. Basic IC Conditions5.1.1Bus Not BusyBoth SDA and SCL remain high.SDASCLSTARTSDA StableSDA may changeSTOPNot BusyAM08X5 DatasheetDS0002V1p1Page 32 of 792014 Ambiq Micro, In
140、c.All rights reserved.5.1.2Start Data TransferA change in the state of SDA from high to low, while SCL is high, defines the START condition. A START condition which occurs after a previous START but before a STOP is called a RESTART condition, and functions exactly like a normal STOP followed by a n
141、ormal START.5.1.3Stop Data TransferA change in the state of SDA from low to high, while SCL is high, defines the STOP condition.5.1.4Data ValidAfter a START condition, SDA is stable for the duration of the high period of SCL. The data on SDA may be changed during the low period of SCL. There is one
142、clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and STOP conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bi
143、t. 5.1.5AcknowledgeEach byte of eight bits is followed by one acknowledge (ACK) bit as shown in Figure 23. This acknowledge bit is a low level driven onto SDA by the receiver, whereas the master generates an extra acknowledge related SCL pulse. A slave receiver which is addressed is obliged to gener
144、ate an acknowledge after the reception of each byte. Also, on a read transfer a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock puls
145、e in such a way that the SDA line is a stable low during the high period of the acknowledge related SCL pulse. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge (a NAK) on the last byte that has been clocked out of the slave. In this case, the tra
146、nsmitter must leave the data line high to enable the master to generate the STOP condition.Figure 23. IC Acknowledge Address OperationFigure 24 illustrates the operation with which the master addresses the AM08X5. After the START condition, a 7-bit address is transmitted MSB first. If this address i
147、s 0b1101001 (0xD2/3), the AM08X5 is selected, the eighth bit indicate a write (RW = 0) or a read (RW = 1) operation and the AM08X5 supplies the ACK. The AM08X5 ignores all other address values and does not respond with an ACK.Figure 24. IC Address OperationSDASCLSTARTMSB (bit 7)Bit 6Bit 0ACK1289A110
148、1000SDASCLRWAM08X5 DatasheetDS0002V1p1Page 33 of 792014 Ambiq Micro, Inc.All rights reserved.5.1.6Offset Address TransmissionIf the RW bit of the Address Operation indicates a write, the next byte transmitted from the master is the Offset Address as shown in Figure 25. This value is loaded into the
149、Address Pointer of the AM08X5.Figure 25. IC Offset Address Transmission5.1.7Write OperationIn a write operation the master transmitter transmits to the AM08X5 slave receiver. The Address Operation has a RW value of 0, and the second byte contains the Offset Address as in Figure 25. The next byte is
150、written to the register selected by the Address Pointer (which was loaded with the Offset Address) and the Address Pointer is incremented. Subsequent transfers write bytes into successive registers until a STOP condition is received, as shown in Figure 26.Figure 26. IC Write Operation5.1.8Read Opera
151、tionIn a read operation, the master first executes an Offset Address Transmission to load the Address Pointer with the desired Offset Address. A subsequent operation will again issue the address of the AM08X5 but with the RW bit as a 1 indicating a read operation. Figure 27 illustrates this transact
152、ion beginning with a RESTART condition, although a STOP followed by a START may also be used. After the address operation, the slave becomes the transmitter and sends the register value from the location pointed to by the Address Pointer, and the Address Pointer is incremented. Subsequent transactio
153、ns produce successive register values, until the master receiver responds with a NAK and/or STOP or RESTART to complete the operation. Because the Address Pointer holds a valid register address, the master may initiate another read sequence at this point without performing another Offset Address ope
154、ration.Figure 27. IC Read OperationA1101000SDASCL0A76543210Offset AddressAddrOffsetSDASCL70Byte NAWAA70Byte N+1A70Byte N+2ASDASCL70Byte NAA70Byte N+1NAddrARRESTARTAddrOffsetAWAM08X5 DatasheetDS0002V1p1Page 34 of 792014 Ambiq Micro, Inc.All rights reserved.5.2SPI InterfaceThe AM08X5 includes a standa
155、rd 4-wire SPI interface. The serial peripheral interface (SPI) bus is intended for synchronous communication between different ICs. It typically consists of four signal lines: serial data input (SDI), serial data output (SDO), serial clock (SCL) and an active low chip enable (nCE). The AM08X5 may be
156、 connected to a master with a 3-wire SPI interface by tying SDI and SDO together. By definition, a device that sends a message is called the “transmitter”, and the device that accepts the message is called the “receiver.” The device that controls the message transfer by driving SCL is called “master
157、.” The devices that are controlled by the master are called “slaves”. The AM08X5 is always a slave device.The nCE input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data transfer between the master and the slave devices via the SDI (master to slave) and SDO
158、 (slave to master) lines. The SCL input, which is generated by the master, is active only during address and data transfer to any device on the SPI bus. The AM08X5 supports clock frequencies up to 2 MHz, and responds to either (CPOL = 0, CPAH = 0 or CPOL = 1, CPAH = 1). For these two modes, input da
159、ta (SDI) is latched in by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL. There is one clock for each bit transferred. Address and data bits are transferred in groups of eight bits. Some MCUs specify CPOL and CPAH in different ways,
160、 so care should be taken when configuring the SPI Master.5.2.1Write OperationFigure 28 illustrates a SPI write operation. The operation is initiated when the nCE signal to the AM08X5 goes low. At that point an 8-bit Address byte is transmitted from the master on the SDI line, with the upper RW bit i
161、ndicating read (if 0) or write (if 1). In this example the RW bit is a one selecting a write operation, and the lower 7 bits of the Address byte contain the Offset Address, which is loaded into the Address Pointer of the AM08X5.Each subsequent byte is loaded into the register selected by the Address
162、 Pointer, and the Address Pointer is incremented. Because the address is only 7 bits long, only the lower 128 registers of the AM08X5 may be accessed via the SPI interface. The operation is terminated by the master by bringing the nCE signal high. Note that the SDO line is not used in a write operat
163、ion and is held in the high impedance state by the AM08X5.Figure 28. SPI Write Operation5.2.2Read OperationFigure 29 illustrates a read operation. The address is transferred from the master to the slave just as it is in a write operation, but in this case the RW bit is a 0 indicating a read. After t
164、he transfer of the last address bit, bit 0, the AM08X5 begins driving data from the register selected by the Address Pointer onto the SDO W654321SDISCL076543210Offset AddressnCEXData Byte N76543210Data Byte N+1XSDOAM08X5 DatasheetDS0002V1p1Page 35 of 792014 Ambiq Micro, Inc.All rights reserved.line,
165、 bit 7 first, and the Address Pointer is incremented. The transfer continues until the master brings the nCE line high.Figure 29. SPI Read Operation5.3XT OscillatorThe AM08X5 includes a very power efficient crystal (XT) oscillator which runs at 32.786 kHz. This oscillator is selected by setting the
166、OSEL bit to 0 and includes a low jitter calibration function.5.4RC OscillatorThe AM08X5 includes an extremely low power RC oscillator which runs at 128 Hz. This oscillator is selected by setting the OSEL bit to 1. Switching between the XT and RC Oscillators is guaranteed to produce less than one sec
167、ond of error in the Calendar Counters. The AM08X5 may be configured to automatically switch to the RC Oscillator when VCC drops below its threshold by setting the AOS bit, and/or be configured to automatically switch if an XT Oscillator failure is detected by setting the FOS bit.5.5RTC Counter Acces
168、sWhen reading any of the counters in the RTC using a burst operation, the 1 Hz and 100 Hz clocks are held off during the access. This guarantees that a single burst will either read or write a consistent timer value (other than the Hundredths Counter see Hundredths Synchronization). There is a watch
169、dog function to ensure that a very long pause on the interface does not cause the RTC to lose a clock. On a write to any of the Calendar Counters, the entire timing chain up to 100 Hz (if the XT Oscillator is selected) or up to 1Hz (if the RC Oscillator is selected) is reset to 0. This guarantees th
170、at the Counters will begin counting immediately after the write is complete, and that in the XT oscillator case the next 100 Hz clock will occur exactly 10 ms later. In the RC Oscillator case, the next 1 Hz clock will occur exactly 1 second later. This allows a burst write to configure all of the Co
171、unters and initiate a precise time start. Note that a Counter write may cause one cycle of a Square Wave output to be of an incorrect period.The WRTC bit must be set in order to write to any of the Counter registers. This bit can be cleared to prevent inadvertent software access to the Counters.5.6H
172、undredths SynchronizationIf the Hundredths Counter is read as part of the counter burst, there is a small probability (approximately 1 in 109) that the Hundredths Counter rollover from 99 to 00 and the Seconds Counter increment will be separated by the read. In this case, correct read information ca
173、n be guaranteed by the following algorithm.1.Read the Counters, using a burst read. If the Hundredths Counter is neither 00 nor 99, the read is cor-rect.2.If the Hundredths Counter was 00, perform the read again. The resulting value from this second read is guaranteed to be correct.3.If the Hundredt
174、hs Counter was 99, perform the read again.R654321SDISCL0Offset AddressnCEXData Byte NData Byte N+17654321076543210SDOXAM08X5 DatasheetDS0002V1p1Page 36 of 792014 Ambiq Micro, Inc.All rights reserved.A.If the Hundredths Counter is still 99, the results of the first read are guaranteed to be correct.
175、Note that it is possible that the second read is not correct.B.If the Hundredths Counter has rolled over to 00, and the Seconds Counter value from the sec-ond read is equal to the Seconds Counter value from the first read plus 1, both reads produced correct values. Alternatively, perform the read ag
176、ain. The resulting value from this third read is guaranteed to be correct.C.If the Hundredths Counter has rolled over to 00, and the Seconds Counter value from the sec-ond read is equal to the Seconds Counter value from the first read, perform the read again. The resulting value from this third read
177、 is guaranteed to be correct.5.7Generating Hundredths of a SecondThe generation of an exact 100 Hz signal for the Hundredths Counter requires a special logic circuit. The 2.048 kHz clock signal is divided by 21 for 12 iterations, and is alternately divided by 20 for 13 iterations. This produces an e
178、ffective division of:(21 * 12 + 20 * 13)/25 = 20.48producing an exact long-term average 100 Hz output, with a maximum jitter of less than 1 ms. The Hundredths Counter is not available when the 128 Hz RC Oscillator is selected.5.8Watchdog TimerThe AM08X5 includes a Watchdog Timer (WDT), which can be
179、configured to generate an interrupt or a reset if it times out. The WDT is controlled by the Watchdog Timer Register (see 0x1B - Watchdog Timer). The RB field selects the frequency at which the timer is decremented, and the BMB field determines the value loaded into the timer when it is restarted. I
180、f the timer reaches a value of zero, the WDS bit determines whether an interrupt is generated in nIRQ. The timer reaching zero sets the WDT flag in the Status Register, which may be cleared by setting the WDT flag to zero.Two actions will restart the WDT timer:1.Writing the Watchdog Timer Register w
181、ith a new watchdog value.2.A change in the level of the WDI pin.If the Watchdog Timer generates an interrupt or reset, the Watchdog Timer Register must be written in order to restart the Watchdog Timer function. If the BMB field is 0, the Watchdog Timer function is disabled.The BMB field describes t
182、he maximum timeout delay. For example, if RB = 01 so that the clock period is 250 ms, a BMB value of 9 implies that the timeout will occur between 2000 ms and 2250 ms after writing the Watchdog Timer Register.5.9Digital Calibration5.9.1XT Oscillator Digital CalibrationIn order to improve the accurac
183、y of the XT oscillator, a Distributed Digital Calibration function is included (see 0x14 - Calibration XT). This function uses a calibration value, OFFSETX, to adjust the clock period over a 16 second or 32 second calibration period. When the 32.786 kHz XT oscillator is selected, the clock at the 16
184、.384 kHz level of the divider chain is modified on a selectable interval. Clock pulses are either added or subtracted to ensure accuracy of the counters. If the CMDX bit is a 0 (normal calibration), OFFSETX cycles of the 16.384 kHz clock are gated (negative calibration) or replaced by 32.786 kHz pul
185、ses (positive calibration) within every 32 second calibration period. In this mode, each step in OFFSETX modifies the clock frequency by 1.907 ppm, with a maximum adjustment of +120/-122 ppm. If the CMDX bit is 1 (coarse calibration), OFFSETX cycles of the 16.384 kHz clock are gated or replaced by t
186、he 32.786 kHz clock within every 16 second calibration period. In this mode, each step in OFFSETX modifies the AM08X5 DatasheetDS0002V1p1Page 37 of 792014 Ambiq Micro, Inc.All rights reserved.clock frequency by 3.814 ppm, with a maximum adjustment of +240/-244 ppm. OFFSETX contains a twos complement
187、 value, so the possible steps are from -64 to +63. Note that unlike other implementations, Distributed Digital Calibration guarantees that the clock is precisely calibrated every 32 seconds with normal calibration and every 16 seconds when coarse calibration is selected.In addition to the normal cal
188、ibration, the AM08X5 also includes an Extended Calibration field to compensate for low capacitance environments. The frequency generated by the Crystal Oscillator may be slowed by 122 ppm times the value in the XTCAL (see 0x1D Oscillator Status Register) field (0, -122,-244 or -366 ppm). The clock i
189、s still precisely calibrated in 16 or 32 seconds. The pulses which are added to or subtracted from the 16.384 kHz clock are spread evenly over each 16 or 32 second period using the Ambiq Micro patented Distributed Calibration algorithm. This ensures that in XT mode the maximum cycle-to-cycle jitter
190、in any clock of a frequency 16.384 kHz or lower caused by calibration will be no more than one 16.384 kHz period. This maximum jitter applies to all clocks in the AM08X5, including the Calendar Counter, Countdown Timer and Watchdog Timer clocks and any clock driven onto the CLKOUT/nIRQ pin.The XT os
191、cillator calibration value is determined by the following process:1.Set the OFFSETX, CMDX and XTCAL register fields to 0 to ensure calibration is not occurring.2.Select the XT oscillator by setting the OSEL bit to 0.3.Configure a square wave output on one of the output pins of frequency Fnom (for ex
192、ample, 16 Hz).4.Measure the frequency Fmeas at the output pin in Hz.5.Compute the adjustment value required in ppm as (32768 Fmeas)*1000000)/32768 = PAdj6.Compute the adjustment value in steps as PAdj/(1000000/219) = PAdj/(1.90735) = Adj7.If Adj -320, the XT frequency is too high to be calibrated8.E
193、lse if Adj -256, set XTCAL = 3, CMDX = 1, OFFSETX = (Adj +192)/29.Else if Adj -192, set XTCAL = 3, CMDX = 0, OFFSETX = Adj +19210. Else if Adj -128, set XTCAL = 2, CMDX = 0, OFFSETX = Adj +12811. Else if Adj -64, set XTCAL = 1, CMDX = 0, OFFSETX = Adj + 6412. Else if Adj 64, set XTCAL = 0, CMDX = 0,
194、 OFFSETX = Adj13. Else if Adj 128, set XTCAL = 0, CMDX = 1, OFFSETX = Adj/214. Else the XT frequency is too low to be calibrated5.9.2RC Oscillator Digital CalibrationThe RC Oscillator has a patented Distributed Digital Calibration function similar to that of the XT Oscillator (see 0x14 - Calibration
195、 XT). However, because the RC Oscillator has a greater fundamental variability, the range of calibration is much larger, with four calibration ranges selected by the CMDR field. When the 128 Hz RC oscillator is selected, the clock at the 64 Hz level of the divider chain is modified on a selectable i
196、nterval using the calibration value OFFSETR. Clock pulses are either added or subtracted to ensure accuracy of the counters. If the CMDR field is 00, OFFSETR cycles of the 64 Hz clock are gated (negative calibration) or replaced by 128 Hz pulses (positive calibration) within every 8,192 second calib
197、ration period. In this mode, each step in OFFSETR modifies the clock frequency by 1.907 ppm, with a maximum adjustment of +15,623/-15,625 ppm (+/- 1.56%). If the CMDR field is 01, OFFSETR cycles of the 64 Hz clock are gated or replaced by the 128 Hz clock within every 4,096 second calibration period
198、. In this mode, each step in OFFSETR modifies the clock frequency by 3.82 ppm, with a maximum adjustment of +31,246/-31,250 ppm (+/-3.12%). If the CMDR field is 10, OFFSETR cycles of the 64 Hz clock are gated (negative calibration) or replaced by 128 Hz pulses (positive calibration) within every 2,0
199、48 second calibration period. In this mode, each step in OFFSETR modifies the clock frequency by 7.64 ppm, with a maximum adjustment of +62,492/-62,500 ppm (+/- 6.25%). If the CMDR field is 11, OFFSETR cycles of the 64 Hz clock are gated or replaced by the 128 Hz clock within every 1,024 second cali
200、bration period. In this mode, each step in OFFSETR modifies the clock frequency by 15.28 ppm, with a maximum adjustment of +124,984/-125,000 ppm (+/-12.5%). OFFSETR contains a twos complement value, so the possible steps are from -8,192 to +8,191.AM08X5 DatasheetDS0002V1p1Page 38 of 792014 Ambiq Mic
201、ro, Inc.All rights reserved.The pulses which are added to or subtracted from the 64 Hz clock are spread evenly over each 8,192 second period using the Ambiq Micro patented Distributed Calibration algorithm. This ensures that in RC mode the maximum cycle-to-cycle jitter in any clock of a frequency 64
202、 Hz or lower caused by calibration will be no more than one 64 Hz period. This maximum jitter applies to all clocks in the AM08X5 including the Calendar Counter, Countdown Timer and Watchdog Timer clocks and any clock driven onto the CLKOUT/nIRQ3 or FOUT/nIRQ pins.The RC oscillator calibration value
203、 is determined by the following process:1.Set the OFFSETR and CMDR register fields to 0 to ensure calibration is not occurring.2.Select the RC oscillator by setting the OSEL bit to 1.3.Configure a square wave output on one of the output pins of frequency Fnom (for example, 16 Hz).4.Measure the frequ
204、ency Fmeas at the output pin in Hz.5.Compute the adjustment value required in ppm as (128 Fmeas)*1000000)/Fmeas = PAdj6.Compute the adjustment value in steps as PAdj/(1000000/219) = PAdj/(1.90735) = Adj7.If Adj -65,536, the RC frequency is too high to be calibrated8.Else if Adj -32,768, set CMDR = 3
205、, OFFSETR = Adj/89.Else if Adj -16,384, set CMDR = 2, OFFSETR = Adj/410. Else if Adj -8,192, set CMDR = 1, OFFSETR = Adj/211. Else if Adj 8192, set CMDR = 0, OFFSETR = Adj12. Else if Adj 16,384, set CMDR = 1, OFFSETR = Adj/213. Else if Adj 32,768, set CMDR = 2, OFFSETR = Adj/414. Else if Adj 65,536,
206、 set CMDR = 3, OFFSETR = Adj/815. Else the RC frequency is too low to be calibrated5.10 AutocalibrationThe AM08X5 includes a very powerful, patented automatic calibration feature, referred to as Autocalibration, which allows the RC Oscillator to be automatically calibrated to the XT Oscillator. The
207、XT Oscillator typically has much better stability than the RC Oscillator but the RC Oscillator requires significantly less power. Autocalibration enables many system configurations to achieve accuracy and stability similar to that of the XT Oscillator while drawing current similar to that of the RC
208、Oscillator. Autocalibration functions in two primary modes: XT Autocalibration Mode and RC Autocalibration Mode. See Ambiq Application Note AN0002 AM08X5/AM18X5 Family Autocalibration for more details.5.10.1 Autocalibration OperationThe Autocalibration operation counts the number of calibrated XT cl
209、ock cycles within a specific period as defined by the RC Oscillator and then loads new values into the Calibration RC Upper and RC Lower registers which will then adjust the RC Oscillator output to match the XT frequency.5.10.2 XT Autocalibration ModeIn XT Autocalibration Mode, the OSEL register bit
210、 is 0 and the AM08X5 uses the XT Oscillator whenever the system power VCC is above the VCCSWF voltage. The RC Oscillator is periodically automatically calibrated to the XT Oscillator. If the AOS bit is set, when VCC drops below the VCCSWF threshold the system will switch to using VBAT, the clocks wi
211、ll begin using the RC Oscillator, Autocalibration will be disabled and the XT Oscillator will be disabled to reduce power requirements. Because the RC Oscillator has been continuously calibrated to the XT Oscillator, it will be very accurate when the switch occurs. When VCC is again above the thresh
212、old, the system will switch back to use the XT Oscillator and restart Autocalibration.AM08X5 DatasheetDS0002V1p1Page 39 of 792014 Ambiq Micro, Inc.All rights reserved.5.10.3 RC Autocalibration ModeIn RC Autocalibration Mode, the OSEL register bit is 1 and the AM08X5 uses the RC Oscillator at all tim
213、es. However, periodically the XT Oscillator is turned on and the RC Oscillator is calibrated to the XT Oscillator. This allows the system to operate most of the time with the XT Oscillator off but allow continuous calibration of the RC Oscillator.5.10.4 Autocalibration Frequency and ControlThe Autoc
214、alibration function is controlled by the ACAL field in the Oscillator Control register as shown in Table 14. If ACAL is 00, no Autocalibration occurs. If ACAL is 10 or 11, Autocalibration occurs every 1024 or 512 seconds, which is referred to as the Autocalibration Period (ACXP). In RC Autocalibrati
215、on Mode, an Autocalibration operation results in the XT Oscillator being enabled for roughly 50 seconds. The 512 second Autocalibration cycles have the XT Oscillator enabled approximately 10% of the time, while 1024 second Autocalibration cycles have the XT Oscillator enabled approximately 4% of the
216、 time.If ACAL is 00 and is then written with a different value, an Autocalibration cycle is immediately executed. This allows Autocalibration to be completely controlled by software. As an example, software could choose to execute an Autocalibration cycle every 2 hours by keeping ACAL at 00, getting
217、 a two hour interrupt using the alarm function, generating an Autocalibration cycle by writing ACAL to 10 or 11, and then returning ACAL to 00.5.10.5 Autocalibration Filter (AF) PinIn order to produce the optimal accuracy for the Autocalibrated RC Oscillator, a filter pin AF is provided. A 47 pF cap
218、acitor should be connected between the AF pin and VSS. In order to enable the filter, the value 0xA0 must be written to the AFCTRL Register at address 0x26 (see 0x26 AFCTRL). The AF filter is disabled by writing 0x00 to the AFCTRL Register. No other values should be written to this register. The Con
219、figuration Key Register must be written with the value 0x9D immediately prior to writing the AFCTRL Register.If the filter capacitor is not connected to the AF pin or is not enabled, the RC Oscillator frequency will typically be between 10 and 50 ppm slower than the XT Oscillator. If the capacitor i
220、s connected to the AF pin and enabled, the RC Oscillator frequency will be within the accuracy range specified in the Oscillator Parameters table of the XT Oscillator.5.10.6 Autocalibration FailIf the operating temperature of the AM08X5 exceeds the Autocalibration range specified in the Oscillator P
221、arameters table or internal adjustment parameters are altered incorrectly, it is possible that the basic frequency of the RC Oscillator is so far away from the nominal 128 Hz value (off by more than 12%) that the RC Calibration circuitry does not have enough range to correctly calibrate the RC Oscil
222、lator. If this situation is detected during an Autocalibration operation, the ACF interrupt flag is set, an external interrupt is generated if the ACIE register bit is set and the Calibration RC registers are not updated.If an Autocalibration failure is detected while running in RC Autocalibration m
223、ode, it is advisable to switch into XT Autocalibration mode to maintain the timing accuracy. This is done by first ensuring a crystal Table 14: Autocalibration ModesACAL ValueCalibration Mode00No Autocalibration01RESERVED10Autocalibrate every 1024seconds (17minutes)11Autocalibrate every 512seconds (
224、9 minutes)AM08X5 DatasheetDS0002V1p1Page 40 of 792014 Ambiq Micro, Inc.All rights reserved.oscillator failure has not occurred (OF flag = 0) and then clearing the OSEL bit. The ACAL field should remain set to either 11 (512 second period) or 10 (1024 second period). After the switch occurs, the OMOD
225、E bit is cleared.While continuing to operate in XT Autocalibration mode, the following steps can be used to determine when it is safe to return to RC Autocalibration mode.1.Clear the ACF flag and ACIE register bit.2.Setup the Countdown Timer or Alarm to interrupt after the next Autocalibration cycle
226、 completes or lon-ger time period.3.After the interrupt occurs, check the status of the ACF flag.4.If the ACF flag is set, it is not safe to return to RC Autocalibration mode. Clear the ACF flag and repeat steps 2-4.5.If the ACF flag is still cleared, it is safe to return to RC Autocalibration mode
227、by setting the OSEL bit.As mentioned in the RC oscillator section, switching between XT and RC oscillators is guaranteed to produce less than one second of error. However, this error needs to be considered and can be safely managed when implementing the steps above. For example, switching between os
228、cillator modes every 48 hours will produce less than 6 ppm of error.5.11 Oscillator Failure DetectionIf the 32.786 kHz XT Oscillator generates clocks at less than 8 kHz for a period of more than 32 ms, the AM08X5 detects an Oscillator Failure. The Oscillator Failure function is controlled by several
229、 bits in the Oscillator Control Register (see 0x1C Oscillator Control) and the Oscillator Status Register (see 0x1D - Oscillator Status Register). The OF flag is set when an Oscillator Failure occurs, and is also set when the AM08X5 initially powers up. If the OFIE bit is set, the OF flag will gener
230、ate an interrupt on IRQ.If the FOS bit is set and the AM08X5 is currently using the XT Oscillator, it will automatically switch to the RC Oscillator on an Oscillator Failure. This guarantees that the system clock will not stop in any case. The OMODE bit indicates the currently selected oscillator, w
231、hich will not match the oscillator requested by the OSEL bit if the XT Oscillator is not running.The OF flag will be set when the AM08X5 powers up, and will also be set whenever the XT Oscillator is stopped. This can happen when the STOP bit is set or the OSEL bit is set to 1 to select the RC Oscill
232、ator. Since the XT Oscillator is stopped in RC Autocalibration mode (see RC Autocalibration Mode), OF will always be set in this mode. The OF flag should be cleared whenever the XT Oscillator is enabled prior to enabling the OF interrupt with OFIE.5.12 InterruptsThe AM08X5 may generate a variety of
233、interrupts which are ORed into the IRQ signal. This may be driven onto either the FOUT/nIRQ pin or the nIRQ2 pin depending on the configuration of the OUT1S and OUT2S fields (see 0x11 - Control2).5.12.1 Interrupt SummaryThe possible interrupts are summarized in Table 15. All enabled interrupts are O
234、Red into the IRQ signal when their respective flags are set. Note that most interrupt outputs use the inverse of the interrupt (i.e. nIRQ). The fields are: Interrupt - the name of the specific interrupt. Function - the functional area which generates the interrupt. Enable - the register bit which en
235、ables the interrupt. Note that for the Watchdog interrupt, WDS is the steering bit, so that the flag generates an interrupt if WDS is 0 and a reset if WDS is 1. In either case, the BMB field must be non-zero to generate the interrupt or reset.AM08X5 DatasheetDS0002V1p1Page 41 of 792014 Ambiq Micro,
236、Inc.All rights reserved. Pulse/Level - some interrupts may be configured to generate a pulse based on the register bits in this column. Level Only implies that only a level may be generated, and the interrupt will only go away when the flag is reset by software. Flag - the register bit which indicat
237、es that the function has occurred. Note that the flag being set will only generate an interrupt signal on an external pin if the corresponding interrupt enable bit is also set.5.12.2 Alarm Interrupt AIRQThe AM08X5 may be configured to generate the AIRQ interrupt when the values in the Time and Date
238、Registers match the values in the Alarm Registers. Which register comparisons are required to generate AIRQ is controlled by the RPT field as described in the Repeat Function table, allowing software to specify the interrupt interval. When an Alarm Interrupt is generated, the ALM flag is set and an
239、external interrupt is generated based on the AIE bit and the pin configuration settings. The IM field controls the period of the external interrupt, including both level and pulse configurations.5.12.3 Countdown Timer Interrupt TIRQThe AM08X5 may be configured to generate the TIRQ interrupt when the
240、 Countdown Timer is enabled by the TE bit and reaches the value of zero, which will set the TIM flag. The TM, TRPT and TFS fields control the interrupt timing (see 0x18 - Countdown Timer Control), and the TIE bit and the pin configuration settings control external interrupt generation. The Timer int
241、errupt is always driven onto the nTIRQ pin if it is available, and may also be driven onto the CLKOUT/nIRQ3 pin by a configuration of the SQFS field (see 0x13 - SQW).5.12.4 Watchdog Timer Interrupt WIRQThe AM08X5 may be configured to generate the WIRQ interrupt when the Watchdog Timer reaches its ti
242、meout value. This sets the WDT flag and is described in Watchdog Timer.5.12.5 Battery Low Interrupt BLIRQThe AM08X5 may be configured to generate the BLIRQ when the voltage on the VBAT pin crosses one of the thresholds set by the BREF field. The polarity of the detected crossing is set by the BPOL b
243、it. 5.12.6 External Interrupts X1IRQ and X2IRQThe AM08X5 may be configured to generate the X1IRQ and X2IRQ interrupts when the EXTI (X1IRQ) or WDI (X2IRQ) inputs toggle. The register bits EX1P and EX2P control whether the rising or falling transitions generate the respective interrupt. Changing EX1P
244、 or EX2P may cause an immediate interrupt, so the corresponding interrupt flag should be cleared after changing these bits.Table 15: Interrupt SummaryInterruptFunctionEnablePulse/LevelFlagAIRQAlarm MatchAIEIMALMTIRQCountdown TimerTIMTMTIMWIRQWatchdog!WDSLevel OnlyWDTBLIRQBattery LowBLIELevel OnlyBLX
245、1IRQExternal 1EX1ELevel OnlyEX1X2IRQExternal 2EX2ELevel OnlyEX2OFIRQOscillator FailOFIELevel OnlyOFACIRQAutocal FailACIELevel OnlyACFAM08X5 DatasheetDS0002V1p1Page 42 of 792014 Ambiq Micro, Inc.All rights reserved.The values of the EXTI and WDI pins may be directly read in the EXIN and WDIN register
246、 bits (see 0x3F - Extension RAM Address). By connecting an input such as a pushbutton to both EXTI and WDI, software can debounce the switch input using software configurable delays.5.12.7 Oscillator Fail Interrupt OFIRQThe AM08X5 may be configured to generate the OFIRQ interrupt if the XT oscillato
247、r fails (see Oscillator Failure Detection).5.12.8 Autocalibration Fail Interrupt ACIRQThe AM08X5 may be configured to generate the ACIRQ interrupt if an Autocalibration operation fails (see Autocalibration Fail).5.12.9 Servicing InterruptsWhen an interrupt is detected, software must clear the interr
248、upt flag in order to prepare for a subsequent interrupt. If only a single interrupt is enabled, software may simply write a zero to the corresponding interrupt flag to clear the interrupt. However, because all of the flags in the Status register are written at once, it is possible to clear an interr
249、upt which has not been detected yet if multiple interrupts are enabled. The ARST register bit is provided to ensure that interrupts are not lost in this case. If ARST is a 1, a read of the Status register will produce the current state of all the interrupt flags and then clear them. An interrupt occ
250、urring at any time relative to this read is guaranteed to either produce a 1 on the Status read, or to set the corresponding flag after the clear caused by the Status read. After servicing all interrupts which produced 1s in the read, software should read the Status register again until it returns a
251、ll zeros in the flags, and service any interrupts with flags of 1.Note that the OF and ACF interrupts are not handled with this process because they are in the Oscillator Status register, but error interrupts are very rare and typically do not create any problems if the interrupts are cleared by wri
252、ting the flag directly.5.13 Power Control and SwitchingThe main power supply to the AM08X5 is the VCC pin, which operates over the range specified by the VCCIO parameter if there are I/O interface operations required, and the range specified by the VCC parameter if only timekeeping operations are re
253、quired. Some versions also include a backup supply which is provided on the VBAT pin and must be in the range specified by the VBAT parameter in order to supply battery power if VCC is below VCCSWF. Refer to the Power Supply and Switchover Parameters table for the specifications related to the power
254、 supplies and switchover. There are several functions which are directly related to the VBAT input. If a single power supply is used it must be connected to the VCC pin.Figure 30 illustrates the various power states and the transitions between them. There are three power states:1.POR the power on re
255、set state. If the AM08X5 is in this state, all registers including the Counter Reg-isters are initialized to their reset values.2.VCC Power the AM08X5 is powered from the VCC supply.3.VBAT Power the AM08X5 is powered from the VBAT supply.Initially, VCC is below the VCCST voltage, VBAT is below the V
256、BATSW voltage and the AM08X5 is in the POR state. VCC rising above the VCCST voltage causes the AM08X5 to enter the VCC Power state. If AM08X5 DatasheetDS0002V1p1Page 43 of 792014 Ambiq Micro, Inc.All rights reserved.VBAT remains below VBATSW, VCC falling below the VCCRST voltage returns the AM08X5
257、to the POR state.Figure 30. Power StatesIf VBAT rises above VBATSW in the POR state, the AM08X5 remains in the POR state. This allows the AM08X5 to be built into a module with a battery included, and minimal current will be drawn from the battery until VCC is applied to the module the first time.If
258、the AM08X5 is in the VCC Power state and VBAT rises above VBATSW, the AM08X5 remains in the VCC Power state but automatic switchover becomes available. VBAT falling below VBATSW has no effect on the power state as long as VCC remains above VCCSWF. If VCC falls below the VCCSWF voltage while VBAT is
259、above VBATSW the AM08X5 switches to the VBAT Power state. VCC rising above VCCSWR returns the AM08X5 to the VCC Power state. There is hysteresis in the rising and falling VCC thresholds to ensure that the AM08X5 does not switch back and forth between the supplies if VCC is near the thresholds. VCCSW
260、F and VCCSWR are independent of the VBAT voltage and allow the AM08X5 to minimize the current drawn from the VBAT supply by switching to VBAT only at the point where VCC is no longer able to power the device.If the AM08X5 is in the VBAT Power state and VBAT falls below VBATRST, the AM08X5 will retur
261、n to the POR state. Whenever the AM08X5 enters the VBAT Power state, the BAT flag in the Status Register (see 0x0F - Status (Read Only) is set and may be polled by software. If the XT oscillator is selected and the AOS bit (see 0x1C - Oscillator Control) is set, the AM08X5 will automatically switch
262、to the RC oscillator in the VBAT Power state in order to conserve battery power. If the IOBM bit (see 0x27 Batmode IO Register) is clear, the I2C or SPI interface is disabled in the VBAT Power state in order to prevent erroneous accesses to the AM08X5 if the bus master loses power. 5.13.1 Battery Lo
263、w Flag and InterruptIf the VBAT voltage drops below the Falling Threshold selected by the BREF field (see 0x21 - BREF Control), the BL flag in the Status Register (see 0x0F - Status (Read Only) is set. If the BLIE interrupt enable bit (see 0x12 - Interrupt Mask) is set, the IRQ interrupt is generate
264、d. This allows software to determine if a backup battery has been drained. Note that the BPOL bit must be set to 0. The algorithm in the Analog Comparator section should be used when configuring the BREF value.If the VBAT voltage is above the rising voltage which corresponds to the current BREF sett
265、ing, BBOD will be set. At that point the VBAT voltage must fall below the falling voltage in order to clear the BBOD bit, set the BAT flag and generate a falling edge BL interrupt. If BBOD is clear, the VBAT voltage must rise above the rising voltage in order to clear the BBOD bit and generate a ris
266、ing edge BL interrupt.VCCVBATPower StatePORVCCSTVCCRSTVCCPowerVCCSTPORVCCSWFVCCPowerVBATPowerVBATSWVCCSWRVCCPowerVCCSWFVBATRSTVBATPowerPORAM08X5 DatasheetDS0002V1p1Page 44 of 792014 Ambiq Micro, Inc.All rights reserved.5.13.2 Analog ComparatorIf a backup battery is not required, the VBAT pin may be
267、used as an analog comparator input. The voltage comparison level is set by the BREF field. If the BPOL bit is 0, the BL flag will be set when the VBAT voltage crosses from above the BREF Falling Threshold to below it. If the BPOL bit is 1, the BL flag will be set when the VBAT voltage crosses from b
268、elow the BREF Rising Threshold to above it. The BBOD bit in the Analog Status Register (see 0x2F Analog Status Register (Read Only) may be read to determine if the VBAT voltage is currently above the BREF threshold (BBOD = 1) or below the threshold (BBOD = 0).There is a reasonably large delay (on th
269、e order of seconds) between changing the BREF field and a valid value of the BBOD bit. Therefore, the algorithm for using the Analog Comparator should comprise the following steps:1.Set the BREF and BPOL fields to the desired values.2.Wait longer than the maximum tBREF time.3.Clear the BL flag, whic
270、h may have been erroneously set as BBOD settles.4.Check the BBOD bit to ensure that the VBAT pin is at a level for which an interrupt can occur. If a fall-ing interrupt is desired (BPOL = 0), BBOD should be 1. If a rising interrupt is desired (BPOL = 1), BBOD should be 0.If the comparison voltage on
271、 the VBAT pin can remain when VCC goes to 0, it is recommended that a Software Reset be generated to the AM08X5 after power up.5.13.3 Pin Control and Leakage ManagementLike most ICs, the AM08X5 may draw unnecessary leakage current if an input pin floats to a value near the threshold or an output pin
272、 is pulled to a power supply. Because external devices may be powered from VCC, extra care must be taken to ensure that any input or output pins are handled correctly to avoid extraneous leakage when VCC goes away and the AM08X5 is powered from VBAT. The Output Control register (see 0x30 Output Cont
273、rol Register), the Batmode IO register (see 0x27 Batmode IO Register) and the Extension RAM Address register (see 0x3F - Extension RAM Address) include bits to manage this leakage, which should be used as follows:1.EXBM should be cleared if the EXTI pin is connected to a device which is powered down
274、 when the AM08X5 is in the VBAT Power state.2.WDBM should be cleared if the WDI pin is connected to a device which is powered down when the AM08X5 is in the VBAT Power state.3.O4BM should be cleared if the CLKOUT/nIRQ3 pin is connected to a device which is powered down when the AM08X5 is in the VBAT
275、 Power state.4.IOBM should be cleared if the I2C or SPI bus master is powered down when the AM08X5 is in the VBAT Power state.5.13.4 Power Up TimingWhen the voltage levels on both the VCC and VBAT signals drop below VCCRST, the AM08X5 will enter the POR state. Once VCC rises above VCCST, the AM08X5
276、will enter the VCC Power state. I/O accesses via the I2C or SPI interface will be disabled for a period of tVH:FOUT. The FOUT/nIRQ pin will be low at power AM08X5 DatasheetDS0002V1p1Page 45 of 792014 Ambiq Micro, Inc.All rights reserved.up, and will go high when tVH:FOUT expires. Software should pol
277、l the FOUT/nIRQ value to determine when the AM08X5 may be accessed. Figure 31 illustrates the timing of a power down/up operation.Figure 31. Power Up Timing5.14 Software ResetSoftware may reset the AM08X5 by writing the special value of 0x3C to the Configuration Key register at offset 0x1F. This wil
278、l provide the equivalent of a power on reset by initializing all of the AM08X5 registers.5.15 Trickle ChargerThe devices supporting the VBAT pin include a trickle charging circuit which allows a battery or supercapacitor connected to the VBAT pin to be charged from the power supply connected to the
279、VCC pin. The circuit of the Trickle Charger is shown in Figure 32. The Trickle Charger configuration is controlled by the Trickle register (see 0x20 - Trickle). The Trickle Charger is enabled if a) the TCS field is 1010, b) the DIODE field is 01 or 10 and c) the ROUT field is not 00. A diode, with a
280、 typical voltage drop of 0.6V, is inserted in the charging path if DIODE is 10. A Schottky diode, with a typical voltage drop of 0.3V, is inserted in the charging path if DIODE is 01. The series current limiting resistor is selected by the ROUT field as shown in the figure. Figure 32. Trickle Charge
281、rStateVCCVBATPwrUpPower DownOperOperNo I/O AccessFOUT/nIRQtVH:FOUTEnable3k11k6kDIODEROUTAM08X5 DatasheetDS0002V1p1Page 46 of 792014 Ambiq Micro, Inc.All rights reserved.6.RegistersRegisters are accessed by selecting a register address and then performing read or write operations. Multiple reads or w
282、rites may be executed in a single access, with the address automatically incrementing after each byte. Table 16 and Table 17 summarize the function of each register. In Table 16, the GPx bits (where x is between 0 and 27) are 28 register bits which may be used as general purpose storage. These bits
283、are not described in the sections below. All of the GPx bits are cleared when the AM08X5 powers up, and they can therefore be used to allow software to determine if a true Power AM08X5On Reset has occurred or hold other initialization data.6.1Register Definitions and Memory MapTable 16: Register Def
284、initions (0x00 to 0x0F)OffsetRegister765432100x00HundredthsSeconds - TenthsSeconds - Hundredths0x01SecondsGP0Seconds - TensSeconds - Ones0x02MinutesGP1Minutes - TensMinutes - Ones0x03Hours (24 hour)GP3GP2Hours - TensHours - Ones0x03Hours (12 hour)GP3GP2AM/PMHours - TensHours - Ones0x04DateGP5GP4Date
285、 - TensDate - Ones0x05MonthsGP8GP7GP6Months - TensMonths - Ones0x06YearsYears - TensYears - Ones0x07WeekdaysGP13GP12GP11GP10GP9Weekdays0x08Hundredths AlarmHundredths Alarm - TenthsHundredths Alarm - Hundredths0x09Seconds AlarmGP14Seconds Alarm - TensSeconds Alarm - Ones0x0AMinutes AlarmGP15Minutes A
286、larm - TensMinutes Alarm - Ones0x0BHours Alarm (24 hour)GP17GP16Hours Alarm - TensHours Alarm - Ones0x0BHours Alarm (12 hour)GP17GP16AM/PMHours Alarm - TensHours Alarm - Ones0x0CDate AlarmGP19GP18Date Alarm - TensDate Alarm - Ones0x0DMonths AlarmGP22GP21GP20Months Alarm - TensMonths Alarm - Ones0x0E
287、Weekdays AlarmGP27GP26GP25GP24GP23Weekdays Alarm0x0FStatusCBBATWDTBLTIMALMEX2EX1AM08X5 DatasheetDS0002V1p1Page 47 of 792014 Ambiq Micro, Inc.All rights reserved.Table 17: Register Definitions (0x10 to 0xFF)OffsetRegister765432100x10Control1STOP12/24OUTBOUT-ARST-WRTC0x11Control2-OUT2SOUT1S0x12IntMask
288、CEBIMBLIETIEAIEEX2EEX1E0x13SQWSQWE-SQFS0x14Cal_XTCMDXOFFSETX0x15Cal_RC_HiCMDROFFSETR13:80x16Cal_RC_LowOFFSETR7:00x17Int Polarity-EX2PEX1P-0x18Timer ControlTETMTRPTRPTTFS0x19TimerCountdown Timer0x1ATimer_InitialTimer Initial Value0x1BWDTWDSBMBWRB0x1COsc. ControlOSELACALAOSFOS-OFIEACIE0x1DOsc. StatusX
289、TCALLKO2OMODE-OFACF0x1ERESERVEDRESERVED0x1FConfiguration KeyConfiguration Key0x20TrickleTCSDIODEROUT0x21BREF ControlBREF-0x22RESERVEDRESERVED0x23RESERVEDRESERVED0x24RESERVEDRESERVED0x25RESERVEDRESERVED0x26AFCTRLAFCTRL0x27BATMODE I/OIOBMRESERVED0x28ID0 (Read only)Part Number MS Byte = 00001000 (0x08)
290、0x29ID1 (Read only)Part Number LS Byte (e.g. 00000101 for AM0805)0x2AID2 (Read only)Revision Major = 00010Revision Minor = 0110x2BID3 (Read only)Lot7:00x2CID4 (Read only)Lot9Unique ID14:80x2DID5 (Read only)Unique ID7:00x2EID6 (Read only)Lot8Wafer0x2FASTATBBODBMIN-VINIT-0x30OCTRLWDBMEXBM-0x3FExtensio
291、n AddressO4BMBPOLWDINEXIN-XADAXADS0x407FRAMNormal RAM Data0x80FFRAMAlternate RAM Data (I2C Mode Only)AM08X5 DatasheetDS0002V1p1Page 48 of 792014 Ambiq Micro, Inc.All rights reserved.6.2Time and Date Registers6.2.10x00 - HundredthsThis register holds the count of hundredths of seconds, in two binary
292、coded decimal (BCD) digits. Values will be from 00 to 99. Note that in order to divide from 32.786 kHz, the hundredths register will not be fully accurate at all times but will be correct every 500 ms. Maximum jitter of this register will be less than 1 ms. The Hundredths Counter is not valid if the
293、 128 Hz RC Oscillator is selected.6.2.20x01 - SecondsThis register holds the count of seconds, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.Table 18: Hundredths RegisterBit76543210NameSeconds - TenthsSeconds - HundredthsReset10011001Table 19: Hundredths Register BitsBitName
294、Function7:4Seconds - TenthsHolds the tenths place in the hundredths counter.3:0Seconds - HundredthsHolds the hundredths place in the hundredths counter.Table 20: Seconds RegisterBit76543210NameGP0Seconds - TensSeconds - OnesReset00000000Table 21: Seconds Register BitsBitNameFunction7GP0Register bit
295、for general purpose use.6:4Seconds - TensHolds the tens place in the seconds counter.3:0Seconds - OnesHolds the ones place in the seconds counter.AM08X5 DatasheetDS0002V1p1Page 49 of 792014 Ambiq Micro, Inc.All rights reserved.6.2.30x02 - MinutesThis register holds the count of minutes, in two binar
296、y coded decimal (BCD) digits. Values will be from 00 to 59.6.2.40x03 - HoursThis register holds the count of hours, in two binary coded decimal (BCD) digits. Values will be from 00 to 23 if the 12/24 bit (see 0x10 - Control1) is clear. If the 12/24 bit is set, the AM/PM bit will be 0 for AM hours an
297、d 1 for PM hours, and hour values will range from 1 to 12.Table 22: Minutes RegisterBit76543210NameGP1Minutes - TensMinutes - OnesReset00000000Table 23: Minutes Register BitsBitNameFunction7GP1Register bit for general purpose use.6:4Minutes - TensHolds the tens place in the minutes counter.3:0Minute
298、s - OnesHolds the ones place in the minutes counter.Table 24: Hours Register (12 Hour Mode)Bit76543210NameGP3GP2AM/PMHours - TensHours - OnesReset00000000Table 25: Hours Register Bits (12 Hour Mode)BitNameFunction7GP3Register bit for general purpose use.6GP2Register bit for general purpose use.5AM/P
299、M0 = AM hours. 1 = PM hours.4Hours - TensHolds the tens place in the hours counter.3:0Hours - OnesHolds the ones place in the hours counter.AM08X5 DatasheetDS0002V1p1Page 50 of 792014 Ambiq Micro, Inc.All rights reserved.6.2.50x04 - DateThis register holds the current day of the month, in two binary
300、 coded decimal (BCD) digits. Values will range from 01 to 31. Leap years are correctly handled from 1900 to 2199.6.2.60x05 - MonthsThis register holds the current month, in two binary coded decimal (BCD) digits. Values will range from 01 to 12.Table 26: Hours Register (24 Hour Mode)Bit76543210NameGP
301、3GP2Hours - TensHours - OnesReset00000000Table 27: Hours Register Bits (24 Hour Mode)BitNameFunction7GP3Register bit for general purpose use.6GP2Register bit for general purpose use.5:4Hours - TensHolds the tens place in the hours counter.3:0Hours - OnesHolds the ones place in the hours counter.Tabl
302、e 28: Date RegisterBit76543210NameGP5GP4Date - TensDate - OnesReset00000001Table 29: Date Register BitsBitNameFunction7GP5Register bit for general purpose use.6GP4Register bit for general purpose use.5:4Date - TensHolds the tens place in the date counter.3:0Date - OnesHolds the ones place in the dat
303、e counter.Table 30: Months RegisterBit76543210NameGP8GP7GP6Months - TensMonths - OnesAM08X5 DatasheetDS0002V1p1Page 51 of 792014 Ambiq Micro, Inc.All rights reserved.6.2.70x06 - YearsThis register holds the current year, in two binary coded decimal (BCD) digits. Values will range from 00 to 99.6.2.8
304、0x07 - WeekdayThis register holds the current day of the week. Values will range from 0 to 6.Reset00000001Table 31: Months Register BitsBitNameFunction7GP8Register bit for general purpose use.6GP7Register bit for general purpose use.5GP6Register bit for general purpose use.4Months - TensHolds the te
305、ns place in the months counter.3:0Months - OnesHolds the ones place in the months counter.Table 32: Years RegisterBit76543210NameYears - TensYears - OnesReset00000000Table 33: Years Register BitsBitNameFunction7:4Years - TensHolds the tens place in the years counter.3:0Years - OnesHolds the ones pla
306、ce in the years counter.Table 34: Weekdays RegisterBit76543210NameGP13GP12GP11GP10GP9WeekdaysReset00000000Table 30: Months RegisterBit76543210AM08X5 DatasheetDS0002V1p1Page 52 of 792014 Ambiq Micro, Inc.All rights reserved.6.3Alarm Registers 6.3.10x08 - Hundredths AlarmThis register holds the alarm
307、value for hundredths of seconds, in two binary coded decimal (BCD) digits. Values will range from 00 to 99.6.3.20x09 - Seconds AlarmThis register holds the alarm value for seconds, in two binary coded decimal (BCD) digits. Values will range from 00 to 59.Table 35: Weekdays Register BitsBitNameFuncti
308、on7GP13Register bit for general purpose use.6GP12Register bit for general purpose use.5GP11Register bit for general purpose use.4GP10Register bit for general purpose use.3GP9Register bit for general purpose use.2:0WeekdaysHolds the weekday counter value.Table 36: Hundredths Alarm RegisterBit76543210
309、NameSeconds Alarm - TenthsSeconds Alarm - HundredthsReset00000000Table 37: Hundredths Alarm Register BitsBitNameFunction7:4Seconds Alarm - TenthsHolds the tenths place for the hundredths alarm.3:0Seconds Alarm - HundredthsHolds the hundredths place for the hundredths alarm.Table 38: Seconds Alarm Re
310、gisterBit76543210NameGP14Seconds Alarm - TensSeconds Alarm - OnesReset00000000AM08X5 DatasheetDS0002V1p1Page 53 of 792014 Ambiq Micro, Inc.All rights reserved.6.3.30x0A - Minutes AlarmThis register holds the alarm value for minutes, in two binary coded decimal (BCD) digits. Values will range from 00
311、 to 59.6.3.40x0B - Hours AlarmThis register holds the alarm value for hours, in two binary coded decimal (BCD) digits. Values will range from 00 to 23 if the 12/24 bit (see 0x10 - Control1) is clear. If the 12/24 bit is set, the AM/PM bit will be 0 for AM hours and 1 for PM hours, and hour values wi
312、ll be from 1 to 12.Table 39: Seconds Alarm Register BitsBitNameFunction7GP14Register bit for general purpose use.6:4Seconds Alarm - TensHolds the tens place for the seconds alarm.3:0Seconds Alarm - OnesHolds the ones place for the seconds alarm.Table 40: Minutes Alarm RegisterBit76543210NameGP15Minu
313、tes Alarm - TensMinutes Alarm - OnesReset00000000Table 41: Minutes Alarm Register BitsBitNameFunction7GP15Register bit for general purpose use.6:4Minute Alarm - TensHolds the tens place for the minutes alarm.3:0Minutes Alarm - OnesHolds the ones place for the minutes alarm.Table 42: Hours Alarm Regi
314、ster (12 Hour Mode)Bit76543210NameGP17GP16AM/PMHours Alarm - TensHours Alarm - OnesReset00000000AM08X5 DatasheetDS0002V1p1Page 54 of 792014 Ambiq Micro, Inc.All rights reserved.6.3.50x0C - Date AlarmThis register holds alarm value for the date, in two binary coded decimal (BCD) digits. Values will r
315、ange from 01 to 31. Leap years are correctly handled from 1900 to 2199.Table 43: Hours Alarm Register Bits (12 Hour Mode)BitNameFunction7GP17Register bit for general purpose use.6GP16Register bit for general purpose use.5AM/PM0 = AM hours. 1 = PM hours.4Hours Alarm - TensHolds the tens place for the
316、 hours alarm.3:0Hour Alarm - OnesHolds the ones place for the hours alarm.Table 44: Hours Alarm Register (24 Hour Mode)Bit76543210NameGP17GP16Hours Alarm - TensHours Alarm - OnesReset00000000Table 45: Hours Alarm Register Bits (24 Hour Mode)BitNameFunction7GP17Register bit for general purpose use.6G
317、P16Register bit for general purpose use.5:4Hours Alarm - TensHolds the tens place for the hours alarm.3:0Hours Alarm - OnesHolds the ones place for the hours alarm.Table 46: Date Alarm RegisterBit76543210NameGP19GP18Date Alarm - TensDate Alarm - OnesReset00000000AM08X5 DatasheetDS0002V1p1Page 55 of
318、792014 Ambiq Micro, Inc.All rights reserved.6.3.60x0D - Months AlarmThis register holds alarm value for months, in two binary coded decimal (BCD) digits. Values will range from 01 to 12.6.3.70x0E - Weekday AlarmThis register holds the alarm value for the day of the week. Values will range from 0 to
319、6.Table 47: Date Alarm Register BitsBitNameFunction7GP19Register bit for general purpose use.6GP18Register bit for general purpose use.5:4Date Alarm - TensHolds the tens place for the date alarm.3:0Date Alarm - OnesHolds the ones place for the date alarm.Table 48: Months Alarm RegisterBit76543210Nam
320、eGP22GP21GP20Months Alarm - TensMonths Alarm - OnesReset00000000Table 49: Months Alarm Register BitsBitNameFunction7GP22Register bit for general purpose use.6GP21Register bit for general purpose use.5GP20Register bit for general purpose use.4Months Alarm - TensHolds the tens place for the months ala
321、rm.3:0Months Alarm - OnesHolds the ones place for the months alarm.Table 50: Weekdays Alarm RegisterBit76543210NameGP27GP26GP25GP24GP23Weekdays AlarmReset00000000AM08X5 DatasheetDS0002V1p1Page 56 of 792014 Ambiq Micro, Inc.All rights reserved.6.4Configuration Registers6.4.10x0F - Status (Read Only)T
322、his register holds a variety of status bits. The register may be written at any time to clear or set any status flag. If the ARST bit is set, any read of the Status Register will clear all of the bits except the CB bit.Table 51: Weekdays Alarm Register BitsBitNameFunction7GP27Register bit for genera
323、l purpose use.6GP26Register bit for general purpose use.5GP25Register bit for general purpose use.4GP24Register bit for general purpose use.3GP23Register bit for general purpose use.2:0Weekdays AlarmHolds the weekdays alarm value.Table 52: Status RegisterBit76543210NameCBBATWDTBLTIMALMEX2EX1Reset000
324、00000Table 53: Status Register BitsBitNameFunction7CBCentury. This bit will be toggled when the Years register rolls over from 99 to 00 if the CEB bit is a 1. A 0 assumes the century is 19xx or 21xx, and a 1 assumes it is 20xx for leap year calculations.6BATSet when the system switches to the VBAT P
325、ower state.5WDTSet when the Watchdog Timer is enabled and is triggered, and the WDS bit is 0.4BLSet if the battery voltage VBAT crosses the reference voltage selected by BREF in the direction selected by BPOL.3TIMSet when the Countdown Timer is enabled and reaches zero.2ALMSet when the Alarm functio
326、n is enabled and all selected Alarm registers match their respective counters.1EX2Set when an external trigger is detected on the WDI pin. The EX2E bit must be set in order for this interrupt to occur, but subsequently clearing EX2E will not automatically clear this flag.0EX1Set when an external tri
327、gger is detected on the EXTI pin. The EX1E bit must be set in order for this interrupt to occur, but subsequently clearing EX1E will not automatically clear this flag.AM08X5 DatasheetDS0002V1p1Page 57 of 792014 Ambiq Micro, Inc.All rights reserved.6.4.20x10 - Control1This register holds some major c
328、ontrol signals.6.4.30x11 - Control2This register holds additional control and configuration signals for the flexible output pins FOUT/nIRQ and nIRQ2. Note that nIRQ2 and FOUT/nIRQ are open drain outputs.Table 54: Control1 RegisterBit76543210NameSTOP12/24OUTBOUTRESERVEDARSTRESERVEDWRTCReset00010001Ta
329、ble 55: Control1 Register BitsBitNameFunction7STOPWhen 1, stops the clocking system. The XT and RC Oscillators are not stopped. In XT Mode the 32.786 kHz clock output will continue to run. In RC Mode, the 128 Hz clock output will con-tinue to run. Other clock output selections will produce static ou
330、tputs. This bit allows the clock system to be precisely started, by setting it to 1 and back to 0. 612/24When 0, the Hours register operates in 24 hour mode. When 1, the Hours register operates in 12 hour mode.5OUTBA static value which may be driven on the nIRQ2 pin. The OUTB bit cannot be set to 1
331、if the LKO2 bit is 1.4OUTA static value which may be driven on the FOUT/nIRQ pin. This bit also defines the default value for the Square Wave output when SQWE is not asserted.3RESERVEDRESERVED2ARSTAuto reset enable. When 1, a read of the Status register will cause any interrupt bits (TIM, BL, ALM, W
332、DT, XT1, XT2) to be cleared. When 0, the bits must be explicitly cleared by writing the Status register.1RESERVEDRESERVED0WRTCWrite RTC. This bit must be set in order to write any of the Counter registers (Hundredths, Sec-onds, Minutes, Hours, Date, Months, Years or Weekdays).Table 56: Control2 Regi
333、sterBit76543210NameRESERVEDOUT2SOUT1SReset00000000Table 57: Control2 Register BitsBitNameFunction7:5RESERVEDRESERVEDAM08X5 DatasheetDS0002V1p1Page 58 of 792014 Ambiq Micro, Inc.All rights reserved.6.4.40x12 - Interrupt MaskThis register holds the interrupt enable bits and other configuration informa
334、tion. 4:2OUT2SControls the function of the nIRQ2 pin, as shown in Table 58.1:0OUT1SControls the function of the FOUT/NIRQ pin, as shown in Table 59.Table 58: nIRQ2 Pin ControlOUT2S ValuenIRQ2 Pin Function000nIRQ if at least one interrupt is enabled, else OUTB001SQW if SQWE = 1, else OUTB010RESERVED0
335、11nAIRQ if AIE is set, else OUTB100TIRQ if TIE is set, else OUTB101nTIRQ if TIE is set, else OUTB110RESERVED111OUTBTable 59: FOUT/nIRQ Pin ControlOUT1S ValueFOUT/nIRQ Pin Function00nIRQ if at least one interrupt is enabled, else OUT01SQW if SQWE = 1, else OUT10SQW if SQWE = 1, else nIRQ if at least
336、one interrupt is enabled, else OUT11nAIRQ if AIE is set, else OUTTable 60: Interrupt Mask RegisterBit76543210NameCEBIMBLIETIEAIEEX2EEX1EReset11100000Table 61: Interrupt Mask Register BitsBitNameFunction7CEBCentury Enable. 0: The CB bit will never be automatically updated.1: The CB bit will toggle wh
337、en the Years register rolls over from 99 to 00.Table 57: Control2 Register BitsBitNameFunctionAM08X5 DatasheetDS0002V1p1Page 59 of 792014 Ambiq Micro, Inc.All rights reserved.6.4.50x13 - SQWThis register holds the control signals for the square wave output. Note that some frequency selections are no
338、t valid if the 128 Hz RC Oscillator is selected. 6:5IMInterrupt Mode.This controls the duration of the nAIRQ interrupt as shown below. The interrupt output always goes high when the corresponding flag in the Status Register is cleared. In order to minimize current drawn by the AM08X5 this field shou
339、ld be kept at 0x3.00: Level (static) for both XT mode and RC mode.01: 1/8192 seconds for XT mode. 1/64 seconds for RC mode.10: 1/64 seconds for both XT mode and RC mode.11: 1/4 seconds for both XT mode and RC mode.4BLIEBattery Low Interrupt Enable.0: Disable the battery low interrupt.1: The battery
340、low detection will generate an interrupt.3TIETimer Interrupt Enable. 0: Disable the timer interrupt.1: The Countdown Timer will generate an IRQ interrupt signal and set the TIM flag when the timer reaches 0.2AIEAlarm Interrupt Enable.0: Disable the alarm interrupt.1: A match of all the enabled alarm
341、 registers will generate an IRQ interrupt signal.1EX2EXT2 Interrupt Enable.0: Disable the XT2 interrupt.1: The WDI input pin will generate the XT2 interrupt when the edge specified by EX2P occurs.0EX1EXT1 Interrupt Enable.0: Disable the XT1 interrupt.1: The EXTI input pin will generate the XT1 inter
342、rupt when the edge specified by EX1P occurs.Table 62: SQW RegisterBit76543210NameSQWERESERVEDSQFSReset00100110Table 63: SQW Register BitsBitNameFunction7SQWEWhen 1, the square wave output is enabled. When 0, the square wave output is held at the value of OUT.6:5RESERVEDRESERVED4:0SQFSSelects the fre
343、quency of the square wave output, as shown in Table 64. Note that some selec-tions are not valid if the 128 Hz oscillator is selected. Some selections also produce short pulses rather than square waves, and are intended primarily for test usage.Table 61: Interrupt Mask Register BitsBitNameFunctionAM
344、08X5 DatasheetDS0002V1p1Page 60 of 792014 Ambiq Micro, Inc.All rights reserved.Table 64: Square Wave Function SelectSQFS ValueSquare Wave Output000001 century(2)0000132.786 kHz(1)000108.192 kHz(1)000114.096 kHz(1)001002.048 kHz(1)001011.024 kHz(1)00110512 Hz(1) Default value00111256 Hz(1)01000128 Hz
345、0100164 Hz0101032 Hz0101116 Hz011008 Hz011014 Hz011102 Hz011111 Hz10000 Hz10001 Hz100101/8 Hz100111/16 Hz101001/32 Hz101011/60 Hz (1 minute)1011016.384 kHz (1)10111100 Hz (1)(2)110001 hour(2)110011 day(2)11010TIRQ11011NOT TIRQ111001 year(2)111011 Hz to Counters(2)111101/32 Hz from Acal(2)111111/8 Hz
346、 from Acal (2)(1)NA if 128 Hz Oscillator selected.(2)Pulses for Test Usage.AM08X5 DatasheetDS0002V1p1Page 61 of 792014 Ambiq Micro, Inc.All rights reserved.6.5Calibration Registers6.5.10x14 - Calibration XTThis register holds the control signals for a digital calibration function of the XT Oscillato
347、r.6.5.20x15 - Calibration RC UpperThis register holds the control signals for the fine digital calibration function of the low power RC Oscillator. This register is initialized with a factory value which calibrates the RC Oscillator to 128 Hz.Table 65: Calibration XT RegisterBit76543210NameCMDXOFFSE
348、TXReset00000000Table 66: Calibration XT Register BitsBitNameFunction7CMDXThe calibration adjust mode. When 0 (Normal Mode), each adjustment step is +/- 2 ppm. When 1 (Coarse Mode), each adjustment step is +/- 4 ppm.6:0OFFSETXThe amount to adjust the effective time. This is a twos complement number w
349、ith a range of -64 to +63 adjustment steps.Table 67: Calibration RC Upper RegisterBit76543210NameCMDROFFSETRUResetPreconfiguredPreconfiguredTable 68: Calibration RC Upper Register BitsBitNameFunction7:6CMDRThe calibration adjust mode for the RC calibration adjustment. CMDR selects the highest fre-qu
350、ency used in the RC Calibration process, as shown in Table 69.5:0OFFSETRUThe upper 6 bits of the OFFSETR field, which is used to set the amount to adjust the effective time. OFFSETR is a twos complement number with a range of -213 to +213-1 adjustment steps.Table 69: CMDR FunctionCMDRCalibration Per
351、iodMinimum AdjustmentMaximum Adjustment008,192 seconds+/-1.91 ppm+/-1.56%014,096 seconds+/-3.82 ppm+/-3.13%AM08X5 DatasheetDS0002V1p1Page 62 of 792014 Ambiq Micro, Inc.All rights reserved.6.5.30x16 - Calibration RC LowerThis register holds the lower 8 bits of the OFFSETR field for the digital calibr
352、ation function of the low power RC Oscillator. This register is initialized with a factory value which calibrates the RC Oscillator to 128 Hz.6.6Interrupt Polarity Control Register6.6.10x17 - Interrupt Polarity ControlThis register controls the external interrupt polarity.102,048 seconds+/-7.64 ppm+
353、/-6.25%111,024 seconds+/-15.28 ppm+/-12.5%Table 70: Calibration RC Lower RegisterBit76543210NameOFFSETRLResetPreconfiguredTable 71: Calibration RC Lower Register BitsBitNameFunction7:0OFFSETRLThe lower 8 bits of the OFFSETR field, which is used to set the amount to adjust the effective time. OFFSETR
354、 is a twos complement number with a range of -213 to +213-1 adjustment steps.Table 72: Interrupt Polarity Control RegisterBit76543210NameRESERVEDEX2PEX1PRESERVEDReset00000000Table 73: Interrupt Polarity Control Register BitsBitNameFunction7:6RESERVEDRESERVED5EX2PWhen 1, the external interrupt XT2 wi
355、ll trigger on a rising edge of the WDI pin. When 0, the external interrupt XT2 will trigger on a falling edge of the WDI pin.Table 69: CMDR FunctionCMDRCalibration PeriodMinimum AdjustmentMaximum AdjustmentAM08X5 DatasheetDS0002V1p1Page 63 of 792014 Ambiq Micro, Inc.All rights reserved.6.7Timer Regi
356、sters6.7.10x18 - Countdown Timer ControlThis register controls the Countdown Timer function. Note that the 00 frequency selection is slightly different depending on whether the 32.786 kHz XT Oscillator or the 128 Hz RC Oscillator is selected. In some RC Oscillator modes, the interrupt pulse output i
357、s specified as RCPLS. In these cases the interrupt output will be a short negative going pulse which is typically between 100 and 400 s. This allows control of external devices which require pulses shorter than the minimum 7.8 ms pulse created directly by the RC Oscillator. 4EX1PWhen 1, the external
358、 interrupt XT1 will trigger on a rising edge of the EXTI pin. When 0, the external interrupt XT1 will trigger on a falling edge of the EXTI pin.3:0RESERVEDRESERVEDTable 74: Countdown Timer Control RegisterBit76543210NameTETMTRPTRPTTFSReset00100011Table 75: Countdown Timer Control Register BitsBitNam
359、eFunction7TETimer Enable. When 1, the Countdown Timer will count down. When 0, the Countdown Timer retains the current value. If TE is 0, the clock to the Timer is disabled for power minimization.6TMTimer Interrupt Mode. Along with TRPT, this controls the Timer Interrupt function as shown in Table 2
360、8. A Level Interrupt will cause the nIRQ signal to be driven low by a Countdown Timer interrupt until the associated flag is cleared. A Pulse interrupt will cause the nIRQ signal to be driven low for the time shown in Table 77 or until the flag is cleared.5TRPTAlong with TM, this controls the repeat
361、 function of the Countdown Timer. If Repeat is selected, the Countdown Timer reloads the value from the Timer_Initial register upon reaching 0, and continues counting. If Single is selected, the Countdown Timer will halt when it reaches zero. This allows the generation of periodic interrupts of virt
362、ually any frequency.4:2RPTThese bits enable the Alarm Interrupt repeat function, as shown in Table 76. HA is the Hun-dredths_Alarm register value.1:0TFSSelect the clock frequency and interrupt pulse width of the Countdown Timer, as defined in Table 77. RCPLS is a 100-400 s pulse.Table 76: Repeat Fun
363、ctionRPTHARepeat When7FFOnce per hundredth (*)Table 73: Interrupt Polarity Control Register BitsBitNameFunctionAM08X5 DatasheetDS0002V1p1Page 64 of 792014 Ambiq Micro, Inc.All rights reserved.7F9-0Once per tenth (*)79-09-0Hundredths match (once per second)6Hundredths and seconds match (once per minu
364、te)5Hundredths, seconds and minutes match (once per hour)4Hundredths, seconds, minutes and hours match (once per day)3Hundredths, seconds, minutes, hours and weekday match (once per week)2Hundredths, seconds, minutes, hours and date match (once per month)1Hundredths, seconds, minutes, hours, date an
365、d month match (once per year)0Alarm Disabled(*)Once per second if 128 Hz Oscillator selectedTable 77: Countdown Timer Function SelectTMTRPTTFSIntRepeatCountdown Timer FrequencyInterrupt Pulse Width32.786 kHz Oscil-lator128 Hz Oscillator32.786 kHz Oscillator128 Hz Oscillator0000PulseSingle4.096 kHz12
366、8 Hz1/4096 s1/128 s0001PulseSingle64 Hz64 Hz1/128 s1/128 s0010PulseSingle1 Hz1 Hz1/64 s1/64 s0011PulseSingle1/60 Hz1/60 Hz1/64 s1/64 s0100PulseRepeat4.096 kHz128 Hz1/4096 s1/128 s0101PulseRepeat64 Hz64 Hz1/128 s1/128 s0110PulseRepeat1 Hz1 Hz1/64 s1/64 s0111PulseRepeat1/60 Hz1/60 Hz1/64 s1/64 s1000Le
367、velSingle4.096 kHz128 HzN/AN/A1001LevelSingle64 Hz64 HzN/AN/A1010LevelSingle1 Hz1 HzN/AN/A1011LevelSingle1/60 Hz1/60 HzN/AN/A1100PulseRepeat4.096 kHz128 Hz1/4096 sRCPLS1101PulseRepeat64 Hz64 Hz1/4096 sRCPLS1110PulseRepeat1 Hz1 Hz1/4096 sRCPLS1111PulseRepeat1/60 Hz1/60 Hz1/4096 sRCPLSTable 76: Repeat
368、 FunctionRPTHARepeat WhenAM08X5 DatasheetDS0002V1p1Page 65 of 792014 Ambiq Micro, Inc.All rights reserved.6.7.20x19 - Countdown TimerThis register holds the current value of the Countdown Timer. It may be loaded with the desired starting value when the Countdown Timer is stopped.6.7.30x1A - Timer In
369、itial ValueThis register holds the value which will be reloaded into the Countdown Timer when it reaches zero if the TRPT bit is a 1. This allows for periodic timer interrupts, and a period of (Timer_initial + 1) * (1/Countdown_frequency).Table 78: Countdown Timer RegisterBit76543210NameCountdown Ti
370、merReset00000000Table 79: Countdown Timer Register BitsBitNameFunction7:0Countdown TimerThe current value of the Countdown Timer.Table 80: Timer Initial Value RegisterBit76543210NameTimer Initial ValueReset00000000Table 81: Timer Initial Value Register BitsBitNameFunction7:0Timer Initial ValueThe va
371、lue reloaded into the Countdown Timer when it reaches zero if the TRPT bit is a 1.AM08X5 DatasheetDS0002V1p1Page 66 of 792014 Ambiq Micro, Inc.All rights reserved.6.7.40x1B - Watchdog TimerThis register controls the Watchdog Timer function.6.8Oscillator Registers6.8.10x1C - Oscillator ControlThis re
372、gister controls the overall Oscillator function. It may only be written if the Configuration Key register contains the value 0xA1. An Autocalibration cycle is initiated immediately whenever this register is written with a value in the ACAL field which is not zero.Table 82: Watchdog Timer RegisterBit
373、76543210NameWDSBMBWRBReset00000000Table 83: Watchdog Timer Register BitsBitNameFunction7WDSWatchdog Steering. When 0, the Watchdog Timer will generate WIRQ when it times out. When 1, the Watchdog Timer will generate a reset when it times out.6:2BMBThe number of clock cycles which must occur before t
374、he Watchdog Timer times out. A value of 00000 disables the Watchdog Timer function.1:0WRBThe clock frequency of the Watchdog Timer, as shown in Table 84.Table 84: Watchdog Timer Frequency SelectWRB ValueWatchdog Timer Frequency0016 Hz014 Hz101 Hz111/4 HzTable 85: Oscillator Control RegisterBit765432
375、10NameOSELACALAOSFOSRESERVEDOFIEACIEReset00000000AM08X5 DatasheetDS0002V1p1Page 67 of 792014 Ambiq Micro, Inc.All rights reserved.6.8.20x1D Oscillator Status RegisterThis register holds several miscellaneous bits used to control and observe the oscillators.Table 86: Oscillator Control Register BitsB
376、itNameFunction7OSELWhen 1, request the RC Oscillator to generate a 128 Hz clock for the timer circuits. When 0, request the XT Oscillator to generate a 32.786 kHz clock to the timer circuit. Note that if the XT Oscillator is not operating, the oscillator switch will not occur. The OMODE field in the
377、 Oscillator Status register indicates the actual oscillator which is selected.6:5ACALControls the automatic calibration function, as described in Autocalibration. 4AOSWhen 1, the oscillator will automatically switch to RC oscillator mode when the system is powered from the battery. When 0, no automa
378、tic switching occurs.3FOSWhen 1, the oscillator will automatically switch to RC oscillator mode when an oscillator failure is detected. When 0, no automatic switching occurs.2RESERVEDRESERVED1OFIEOscillator Fail interrupt enable. When 1, an Oscillator Failure will generate an IRQ signal.0ACIEWhen 1,
379、 an Autocalibration Failure will generate an interrupt.Table 87: Oscillator Status RegisterBit76543210NameXTCALLKO2OMODERESERVEDOFACFReset00100010Table 88: Oscillator Status Register BitsBitNameFunction7:6XTCALExtended Crystal Calibration. This field defines a value by which the Crystal Oscillator i
380、s adjusted to compensate for low capacitance crystals, independent of the normal Crystal Calibration func-tion controlled by the Calibration XT Register. The frequency generated by the Crystal Oscillator is slowed by 122 ppm times the value in the XTCAL field (0, -122,-244 or -366 ppm).5LKO2Lock OUT
381、2. If this bit is a 1, the OUTB register bit (see Section 7.3.2) cannot be set to 1. This is typically used when OUT2 is configured as a power switch, and setting OUTB to a 1 would turn off the switch.4OMODE(read only) Oscillator Mode. This bit is a 1 if the RC Oscillator is selected to drive the in
382、ternal clocks, and a 0 if the Crystal Oscillator is selected. If the STOP bit is set, the OMODE bit is invalid.3:2RESERVED RESERVED 1OFOscillator Failure. This bit is set on a power on reset, when both the system and battery voltages have dropped below acceptable levels. It is also set if an Oscilla
383、tor Failure occurs, indicating that the crystal oscillator is running at less than 8 kHz. It can be cleared by writing a 0 to the bit.0ACFSet when an Autocalibration Failure occurs, indicating that either the RC Oscillator frequency is too different from 128 Hz to be correctly calibrated or the XT O
384、scillator did not start.AM08X5 DatasheetDS0002V1p1Page 68 of 792014 Ambiq Micro, Inc.All rights reserved.6.9Miscellaneous Registers6.9.10x1F - Configuration KeyThis register contains the Configuration Key, which must be written with specific values in order to access some registers and functions. Th
385、e Configuration Key is reset to 0x00 on any register write.1.Writing a value of 0xA1 enables write access to the Oscillator Control register2.Writing a value of 0x3C does not update the Configuration Key register, but generates a Software Reset (see Software Reset). 3.Writing a value of 0x9D enables
386、 write access to the Trickle Register (0x20), the BREF Register (0x21), the AFCTRL Register (0x26), the Batmode I/O Register (0x27) and the Output Control Regis-ter (0x30).6.10 Analog Control Registers6.10.1 0x20 - TrickleThis register controls the Trickle Charger. The Key Register must be written w
387、ith the value 0x9D in order to enable access to this register.Table 89: Configuration Key RegisterBit76543210NameConfiguration KeyReset00000000Table 90: Configuration Key Register BitsBitNameFunction7:0Configuration KeyWritten with specific values in order to access some registers and functions.Tabl
388、e 91: Trickle RegisterBit76543210NameTCSDIODEROUTReset00000000Table 92: Trickle Register BitsBitNameFunction7:4TCSA value of 1010 enables the trickle charge function. All other values disable the Trickle Charger.3:2DIODEDiode Select. A value of 10 inserts a standard diode into the trickle charge cir
389、cuit, with a voltage drop of 0.6V. A value of 01 inserts a schottky diode into the trickle charge circuit, with a voltage drop of 0.3V. Other values disable the Trickle Charger.1:0ROUTOutput Resistor. This selects the output resistor of the trickle charge circuit, as shown in Table 93.AM08X5 Datashe
390、etDS0002V1p1Page 69 of 792014 Ambiq Micro, Inc.All rights reserved.6.10.2 0x21 - BREF ControlThis register controls the reference voltages used in the Wakeup Control system. The Key Register must be written with the value 0x9D in order to enable access to this register.6.10.3 0x26 AFCTRLThis registe
391、r holds the enable code for the Autocalibration Filter (AF) filter capacitor connected to the AF pin. Writing the value 0xA0 to this register enables the AF pin. Writing the value 0x00 to this register Table 93: Trickle Charge Output ResistorROUT ValueSeries Resistor00Disable013 K106 K1111 KTable 94
392、: BREF Control RegisterBit76543210NameBREFRESERVEDReset11110000Table 95: BREF Control Register BitsBitNameFunction7:4BREFThis selects the voltage reference which is compared to the battery voltage VBAT to produce the BBOD signal. Typical values are shown in Table 96. The valid BREF values are 0x7, 0
393、xB, 0xD, and 0xF. The reset value is 0xF. All other values are RESERVED.3:0RESERVEDRESERVEDTable 96: VBAT Reference VoltageBREF ValueVBAT Falling Voltage (TYP)VBAT Rising Voltage (TYP)01112.5V3.0V10112.1V2.5V11011.8V2.2V11111.4V1.6VAM08X5 DatasheetDS0002V1p1Page 70 of 792014 Ambiq Micro, Inc.All rig
394、hts reserved.disables the AF pin. No other value may be written to this register. The Configuration Key Register must be written with the value 0x9D prior to writing the AFCTRL Register.6.10.4 0x27 Batmode IO RegisterThis register holds the IOBM bit which controls the enabling and disabling of the I
395、/O interface when a Brownout Detection occurs. It may only be written if the Configuration Key register contains the value 0x9D. All undefined bits must be written with 0.6.10.5 0x2F Analog Status Register (Read Only)This register holds eight status bits which indicate the voltage levels of the VCC
396、and VBAT power inputs.Table 97: AFCTRL RegisterBit76543210NameAFCTRLReset00000000Table 98: AFCTRL Register BitsBitNameFunction7:0AFCTRLIf 0xA0, enable the AF pin. If 0x00, disable the AF pin.Table 99: Batmode IO RegisterBit76543210NameIOBMRESERVEDReset10000000Table 100: Batmode IO Register BitsBitNa
397、meFunction7IOBMIf 1, the AM08X5 will not disable the I/O interface even if VCC goes away and VBAT is still present. This allows external access while the AM08X5 is powered by VBAT.6:0RESERVEDRESERVED - must write only 0000000.Table 101: Analog Status RegisterBit76543210NameBBODBMINRESERVEDVINITRESER
398、VEDAM08X5 DatasheetDS0002V1p1Page 71 of 792014 Ambiq Micro, Inc.All rights reserved.6.10.6 0x30 Output Control RegisterThis register holds bits which control the behavior of the I/O pins under various power down conditions. The Key Register must be written with the value 0x9D in order to enable acce
399、ss to this register.ResetTable 102: Analog Status Register BitsBitNameFunction7BBODIf 1, the VBAT input voltage is above the BREF threshold.6BMINIf 1, the VBAT input voltage is above the minimum operating voltage (1.2 V).5:2RESERVEDRESERVED1VINITIf 1, the VCC input voltage is above the minimum power
400、 up voltage (1.6 V).0RESERVEDRESERVED Table 103: Output Control RegisterBit76543210NameWDBMEXBMRESERVEDReset00000000Table 104: Output Control Register BitsBitNameFunction7WDBMIf 1, the WDI input is enabled when the AM08X5 is powered from VBAT. If 0, the WDI input is dis-abled when the AM08X5 is powe
401、red from VBAT.6EXBMIf 1, the EXTI input is enabled when the AM08X5 is powered from VBAT. If 0, the EXTI input is dis-abled when the AM08X5 is powered from VBAT.5:0RESERVEDRESERVEDTable 101: Analog Status RegisterBit76543210AM08X5 DatasheetDS0002V1p1Page 72 of 792014 Ambiq Micro, Inc.All rights reser
402、ved.6.11 ID Registers6.11.1 0x28 ID0 - Part Number Upper Register (Read Only)This register holds the upper eight bits of the part number in BCD format, which is always 0x08 for the AM08X5 family.6.11.2 0x29 ID1 - Part Number Lower Register (Read Only)This register holds the lower eight bits of the p
403、art number in BCD format.6.11.3 0x2A ID2 - Part Revision (Read Only)This register holds the Revision number of the part.Table 105: 28 ID0 Part Number Upper RegisterBit76543210NamePart Number - Digit 3 Part Number - Digit 2Reset00001000Table 106: 28 ID1 Part Number Lower RegisterBit76543210NamePart N
404、umber - Digit 1 Part Number - Digit 0ResetPreconfigured Digit 1Preconfigured Digit 0Table 107: 2A ID2 Part Revision RegisterBit76543210NameMAJORMINORReset00010011Table 108: 2A ID2 Part Revision Register BitsBitNameFunction7:3MAJORThis field holds the major revision of the AM08X5.2:0MINORThis field h
405、olds the minor revision of the AM08X5.AM08X5 DatasheetDS0002V1p1Page 73 of 792014 Ambiq Micro, Inc.All rights reserved.6.11.4 0x2B ID3 Lot Lower (Read Only)This register holds the lower 8 bits of the manufacturing lot number.6.11.5 0x2C ID4 ID Upper (Read Only)This register holds part of the manufac
406、turing information of the part, including bit 9 of the manufacturing lot number and the upper 7 bits of the unique part identifier. The 15-bit ID field contains a unique value for each AM08X5 part. 6.11.6 0x2D ID5 Unique Lower (Read Only)This register holds the lower 8 bits of the unique part identi
407、fier. The 15-bit ID field contains a unique value for each AM08X5 part. Table 109: 2B ID3 Lot Lower RegisterBit76543210NameLot7:0 ResetPreconfigured Lot NumberTable 110: 2B ID3 Lot Lower Register BitsBitNameFunction7:0Lot7:0This field holds the lower 8 bits of the manufacturing lot number.Table 111:
408、 2C ID4 ID Upper RegisterBit76543210NameLot9ID14:8ResetPreconfigured ValueTable 112: 2C ID4 ID Upper Register BitsBitNameFunction7Lot9This field holds bit 9 of the manufacturing lot number.1:0ID14:8This field holds the upper 7 bits of the unique part ID.Table 113: 2D ID5 ID Lower RegisterBit76543210
409、NameID7:0ResetPreconfigured ValueAM08X5 DatasheetDS0002V1p1Page 74 of 792014 Ambiq Micro, Inc.All rights reserved.6.11.7 0x2E ID6 Wafer (Read Only)6.12 Ram Registers6.12.1 0x3F - Extension RAM AddressThis register controls access to the Extension RAM, and includes some miscellaneous control bits.Tab
410、le 114: 2D ID5 ID Lower Register BitsBitNameFunction7:0ID7:0This field holds the lower 8 bits of the unique part ID.Table 115: 2E ID6 Wafer RegisterBit76543210NameLot8WaferRESERVEDResetPreconfigured ValueTable 116: 2E ID6 Wafer Register BitsBitNameFunction7Lot8This field holds bit 8 of the manufactu
411、ring lot number.6:2WaferThis field holds the manufacturing wafer number.1:0RESERVEDRESERVEDTable 117: 3F Extension RAM Address RegisterBit76543210NameO4BMBPOLWDINEXINRSVDXADAXADSReset00Read Only0000Table 118: 3F Extension RAM Address Register BitsBitNameFunction7O4BMIf 1, the CLKOUT/nIRQ3 output is
412、enabled when the AM08X5 is powered from VBAT. If 0, the CLK-OUT/nIRQ3 output is completely disconnected when the AM08X5 is powered from VBAT.6BPOLBL Polarity. When 0, the Battery Low flag BL is set when the VBAT voltage goes below the BREF threshold. When 1, the Battery Low flag BL is set when the V
413、BAT voltage goes above the BREF threshold.5WDIN(read only) this bit supplies the current level of the WDI pin.4EXIN(read only) this bit supplies the current level of the EXTI pin.AM08X5 DatasheetDS0002V1p1Page 75 of 792014 Ambiq Micro, Inc.All rights reserved.6.12.2 0x40 - 0x7F Standard RAM64 bytes
414、of RAM space which may be accessed in either I2C or SPI interface mode. The data in the RAM is held when using battery power. The upper 2 bits of the RAM address are taken from the XADS field, and the lower 6 bits are taken from the address offset, supporting a total RAM of 256 bytes. The initial va
415、lues of the RAM locations are undefined.6.12.3 0x80 - 0xFF Alternate RAM128 bytes of RAM which may be accessed only in I2C interface mode. The data in the RAM is held when using battery power. The upper bit of the RAM address is taken from the XADA field, and the lower 7 bits are taken from the addr
416、ess offset, supporting a total RAM of 256 bytes. The initial values of the RAM locations are undefined.3RSVDRESERVED.2XADAThis field supplies the upper bit for addresses to the Alternate RAM address space.1:0XADSThis field supplies the upper two address bits for the Standard RAM address space.Table
417、118: 3F Extension RAM Address Register BitsBitNameFunctionAM08X5 DatasheetDS0002V1p1Page 76 of 792014 Ambiq Micro, Inc.All rights reserved.7.Package Mechanical InformationFigure 33 illustrates the package mechanical information.Figure 33. Package Mechanical Diagram3.00 0.053.00 0.050.85 0.05SeatingP
418、lane0.20REF0.350.05x161.80 0.101.80 0.100.25REFPACKAGETOPVIEWPACKAGESIDEVIEWPACKAGEBOTTOMVIEWThermalPad1DrawingNotes:1. Alldimensionsareinmillimeters.2. Thesedrawingsaresubjecttochangewithoutnotice.3. QuadFlatpack,Noleads(QFN)packageconfiguration.4. Thepackagethermalpadmustbesolderedtotheboardforcon
419、nectivityandmechanicalperformance.5. Customersshouldcontacttheirboardfabricatorforminimumsoldermasktolerancesbetweensignalpads.EXAMPLEPCBLANDPATTERN0.50BSCEXAMPLESOLDERSTENCIL10.520.30x161.801.800.502.263.300.480.26x160.502.303.260.200.200.500.50Pin1MarkingAM08X5 DatasheetDS0002V1p1Page 77 of 792014
420、 Ambiq Micro, Inc.All rights reserved.8.Reflow ProfileFigure 34 illustrates the reflow soldering requirements.Figure 34. Reflow Soldering DiagramTable 119: Reflow Soldering RequirementsProfile FeatureRequirementPreheat/SoakTemperature Min (Tsmin)Temperature Max (Tsmax)Time (ts) from (Tsmin to Tsmax)
421、150 C200 C60-120 secondsRamp-up rate (TL to Tp)3 C/second max.Liquidous temperature (TL)Time (tL) maintained above TL217 C60-150 secondsPeak package body temperature (Tp)260 C max.Time (tp) within 5 C of Tp30 seconds max.Ramp-down rate (Tp to TL)6 C/second max.Time 25 C to peak temperature8 minutes
422、max.AM08X5 DatasheetDS0002V1p1Page 78 of 792014 Ambiq Micro, Inc.All rights reserved.9.Ordering Information10. Document Revision HistoryTable 120: Ordering InformationDeviceAM08X5 Orderable Part Numbers PackageTemperature RangeMSL Level(2)StandardTape and Reel - 3000 pcs.AM0805AM0805AQAM0805AQPb-Fre
423、e(1) 16-Pin QFN 3 x 3 mm-40 to +85 C1AM0815AM0815AQAM0815AQ(1)Compliant and certified with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in raw homogeneous materials. The package was designed to be soldered at high temperatures (per
424、 reflow profile) and can be used in specified lead-free processes.(2)Moisture Sensitivity Level rating according to the JEDEC J-STD-020D industry standard classifications.Table 121: Document Revision HistoryRev #Description0.00Initial version0.90Initial preliminary release0.91Formating changes. Upda
425、ted values in electrical specification tables. Added AF pin and description. Added AM18XX VBAT application example. Removed OUTPP, XTF, and XEN bits. Updated BREF selection tables. Added minimum I2C/SPI bus frequencies. Added tXTST parameter. Added autocalibration temperature range of operation. Add
426、ed PSW pulsed current spec. Added AFCTRL register. Added 1.5k ohm VBAT series imped-ance requirement. Updated trickle charger information to include schottky diode. Added current vs. tempera-ture curves for VCC and VBAT. Added RC frequency vs. temperature curves. Updated orderable part number inform
427、ation. Updated register reset values.1.0- Added limits and/or temperature range specifications for the following parameters:VCC,ABSMAX, VBAT,ABSMAX, VCCIO, VCCRST, VCCSWR, VCCSWF, VCCRS, VCCFS, VBATRST, VT+, VT-, ILEAK, IOH, IOL, RDSON, IOLEAK, CEX, OAXT, FRCC, FRCU, TAC, IVCC:I2C, IVCC:SPIW, IVCC:S
428、PIR, IVCC:XT, IVCC:RC, IVCC:ACAL, IVCC:CK32, IVCC:CLK128, IVBAT:XT, IVBAT:RC, IVBAT:ACAL, IVBAT:VCC, VBRF, VBRR, VBRH, TBR, tLOW:VCC, tVL:FOUT, tVH:FOUT, tXTST, tVL:NRST, tVH:NRST, tRL:NRST, tRH:NRST- Removed tBREF parameter- Additional note on autocalibration operating temperature range in the elec
429、trical specification section- Added additional description to the Autocalibration Fail section- Updated XT digital calibration adjustment value equation- Removed VCCRS parameter as there is no requirement for the VCC rising slew rate- Added curves to the electrical specification section: VCC Current
430、 vs. Voltage in different operating modes, VCC Current vs. Voltage During I2C/SPI burst read/write, VCC Current vs. Voltage with 32.768kHz Clock Out-put, VBAT Current vs. Voltage in different operating modes, VBAT current vs. Voltage in VCC power state- Removed typical values at 1.5V and 3.6V in VCC
431、 supply current table and replaced with VCC supply current vs. voltage curves- Removed typical values at 1.5V and 3.6V in VBAT supply current table and replaced with VBAT supply cur-rent vs. voltage curve- Updated orderable part numbers1.1- Reduced part selection to AM0805 and AM0815- Updated RCPLS
432、value to be consistent across the datasheet- Renamed datasheet to AM08X5AM08X5 DatasheetDS0002V1p1Page 79 of 792014 Ambiq Micro, Inc.All rights reserved.11. Contact Information12. Legal Information and DisclaimersAMBIQ MICRO INTENDS FOR THE CONTENT CONTAINED IN THE DOCUMENT TO BE ACCURATE AND RELIAB
433、LE. THIS CONTENT MAY, HOW-EVER, CONTAIN TECHNICAL INACCURACIES, TYPOGRAPHICAL ERRORS OR OTHER MISTAKES. AMBIQ MICRO MAY MAKE CORRECTIONS OR OTHER CHANGES TO THIS CONTENT AT ANY TIME. AMBIQ MICRO AND ITS SUPPLIERS RESERVE THE RIGHT TO MAKE CORRECTIONS, MODIFICATIONS, ENHANCEMENTS, IMPROVEMENTS AND OT
434、HER CHANGES TO ITS PRODUCTS, PROGRAMS AND SERVICES AT ANY TIME OR TO DISCONTINUE ANY PRODUCTS, PROGRAMS, OR SERVICES WITHOUT NOTICE.THE CONTENT IN THIS DOCUMENT IS PROVIDED AS IS. AMBIQ MICRO AND ITS RESPECTIVE SUPPLIERS MAKE NO REPRESENTATIONS ABOUT THE SUITABILITY OF THIS CONTENT FOR ANY PURPOSE A
435、ND DISCLAIM ALL WARRANTIES AND CONDITIONS WITH REGARD TO THIS CONTENT, INCLUDING BUT NOT LIMITED TO, ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHT.AMBIQ MICRO DOES NOT WARRANT OR R
436、EPRESENT THAT ANY LICENSE, EITHER EXPRESS OR IMPLIED, IS GRANTED UNDER ANY PAT-ENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT OF AMBIQ MICRO COVERING OR RELATING TO THIS CONTENT OR ANY COMBINATION, MACHINE, OR PROCESS TO WHICH THIS CONTENT RELATE OR WITH WHICH THIS CONTE
437、NT MAY BE USED.USE OF THE INFORMATION IN THIS DOCUMENT MAY REQUIRE A LICENSE FROM A THIRD PARTY UNDER THE PATENTS OR OTHER INTEL-LECTUAL PROPERTY OF THAT THIRD PARTY, OR A LICENSE FROM AMBIQ MICRO UNDER THE PATENTS OR OTHER INTELLECTUAL PROP-ERTY OF AMBIQ MICRO.INFORMATION IN THIS DOCUMENT IS PROVID
438、ED SOLELY TO ENABLE SYSTEM AND SOFTWARE IMPLEMENTERS TO USE AMBIQ MICRO PRODUCTS. THERE ARE NO EXPRESS OR IMPLIED COPYRIGHT LICENSES GRANTED HEREUNDER TO DESIGN OR FABRICATE ANY INTE-GRATED CIRCUITS OR INTEGRATED CIRCUITS BASED ON THE INFORMATION IN THIS DOCUMENT. AMBIQ MICRO RESERVES THE RIGHT TO M
439、AKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN. AMBIQ MICRO MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR DOES AMBIQ MICRO ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT, AND S
440、PECIFICALLY DISCLAIMS ANY AND ALL LIABILITY, INCLUDING WITHOUT LIMITATION CONSEQUENTIAL OR INCIDENTAL DAMAGES. “TYPICAL” PARAMETERS WHICH MAY BE PRO-VIDED IN AMBIQ MICRO DATA SHEETS AND/OR SPECIFICATIONS CAN AND DO VARY IN DIFFERENT APPLICATIONS AND ACTUAL PERFOR-MANCE MAY VARY OVER TIME. ALL OPERAT
441、ING PARAMETERS, INCLUDING “TYPICALS” MUST BE VALIDATED FOR EACH CUSTOMER APPLICATION BY CUSTOMERS TECHNICAL EXPERTS. AMBIQ MICRO DOES NOT CONVEY ANY LICENSE UNDER NEITHER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS. AMBIQ MICRO PRODUCTS ARE NOT DESIGNED, INTENDED, OR AUTHORIZED FOR USE AS COMPO-NENTS
442、 IN SYSTEMS INTENDED FOR SURGICAL IMPLANT INTO THE BODY, OR OTHER APPLICATIONS INTENDED TO SUPPORT OR SUSTAIN LIFE, OR FOR ANY OTHER APPLICATION IN WHICH THE FAILURE OF THE AMBIQ MICRO PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. SHOULD BUYER PURCHASE OR USE AMBIQ MICRO
443、 PRODUCTS FOR ANY SUCH UNINTENDED OR UNAUTHORIZED APPLICATION, BUYER SHALL INDEMNIFY AND HOLD AMBIQ MICRO AND ITS OFFICERS, EMPLOYEES, SUBSIDIARIES, AFFILIATES, AND DISTRIBUTORS HARMLESS AGAINST ALL CLAIMS, COSTS, DAMAGES, AND EXPENSES, AND REASONABLE ATTORNEY FEES ARISING OUT OF, DIRECTLY OR INDIRE
444、CTLY, ANY CLAIM OF PERSONAL INJURY OR DEATH ASSOCIATED WITH SUCH UNINTENDED OR UNAUTHORIZED USE, EVEN IF SUCH CLAIM ALLEGES THAT AMBIQ MICRO WAS NEGLIGENT REGARDING THE DESIGN OR MANUFAC-TURE OF THE PART.AddressAmbiq Micro, Inc.11305 Four Points Drive Building 2, Suite 250Austin, TX 78726Phone+1 (512) 879-2850WGeneral ISTechnical S
