数字电路教学课件:chapter5-1

上传人:汽*** 文档编号:571672063 上传时间:2024-08-11 格式:PPT 页数:40 大小:505.50KB
返回 下载 相关 举报
数字电路教学课件:chapter5-1_第1页
第1页 / 共40页
数字电路教学课件:chapter5-1_第2页
第2页 / 共40页
数字电路教学课件:chapter5-1_第3页
第3页 / 共40页
数字电路教学课件:chapter5-1_第4页
第4页 / 共40页
数字电路教学课件:chapter5-1_第5页
第5页 / 共40页
点击查看更多>>
资源描述

《数字电路教学课件:chapter5-1》由会员分享,可在线阅读,更多相关《数字电路教学课件:chapter5-1(40页珍藏版)》请在金锄头文库上搜索。

1、Synchronous Sequential CircuitChapter 6AnalysisAnalysisAnalyze existing circuits to determine their functionlSynchronous sequential circuitlThe basic modeling structurelTwo circuit models: Mealy model & Moore modellThree approach used to describe the circuit:lLogic function equation l State table l

2、State diagram2 /40Universal modelSystem output VariablesO0OmErExcitation VariablesE0Combinational Combinational logiclogicSystem Input VariablesI0InS0SxState VariablesMemoryFlip-flopsCLOCK3 /40Analysis principlelDetermine the system variables: input, state and output.lAssign names to the variables i

3、f they are not clear from the logic diagram.lDetermine the flip-flop type. Write the characteristics equations.lWrite the excitation equations by inspection from the logic diagram.lWrite the output variable equations. Determine whether the circuit is a Mealy or a Moore machine.4 /40Analysis principl

4、elMealy model machinelE = f( I, St )lSt+1 = f( St, E ) flip-flop characteristics equationlO = g( I, St )lMoore model machinelE = f( I, St )lSt+1 = f( St, E ) flip-flop characteristics equationlO = g(St )5 /40lWrite the next state equations for each state variable, using the flip-flop characteristics

5、 equation and the circuit excitation equations, or construct the excitation table from the excitation equations.lConstruct a transition table. Identify all of the states possible for a given number of state variables.lAssign symbols to the states and construct a state table or state diagram.lWhen po

6、ssible, construct a timing diagram.Analysis principle6 /40Logic circuitOutput variable equations &Excitation equationsNext-state truth tableNext-state equationsflip-flop Characteristic tableState diagram &State tableDescribe the circuit by a timing diagram and statementFlip-flop Characteristic equat

7、iontabletablealgebraalgebraAnalysis flowchart7 /40Example 6.2Start/stop sensorSTARTSTARTNSTOPSTOPNt1t2LVprojectile = L/ (t2-t1)8 /40lStart/ stop sensorslAs the bullet passes over the start sensor, the start signal (SRT)(SRT) is generated.lWhen the same bullet passes over the stop sensor, the stop si

8、gnal (STP)(STP) is generated.Example 6.2Start/stop sensorSTART (SRT)STARTNSTOP (STP)STOP (STP)STOPN9 /40Example 6.2lBCD counter : lt2-t1 lmeasure the elapsed time of the bullet directly by counting the number of clock pulse. 10 /40Example 6.2lBCD counterlClock inputlClock generator : 2MHz Square-wav

9、e lClock frequency divider : 1MHz Square-wave lOutput : LED displaylEnable input: Reset/latchlSequential circuit controllerlSRT, SPT11 /40lSequential circuit controllerlThe external input variables : SRT, SPTSRT, SPTlThe external output variables Clock enable : CENCEN (U3D)Reset enable : CRSTCRST (U

10、2A)Latch enable : CLTCHCLTCH (U2B)lThe excitation variables J1, K1J1, K1 (U1A-U2C/U2D) J2, K2J2, K2 (U6A-U3A/U3B)lThe state variables F1, F1F1, F1 (U1A) F2, F2F2, F2 (U6A)Example 6.212 /40lSequential circuit controllerlThe external output variables lClock enable : CEN =F2CEN =F2 F1F1 (U3D)lReset ena

11、ble : CRST =F2CRST =F2 F1F1 (U2A)lLatch enable : CLTCH =F2CLTCH =F2 F1F1 (U2B)lThe excitation variableslJ1=SRTF2 , K1=STPF2 (U1A-U2C/U2D)lJ2=SRTF1 , K2=STPF1 (U6A-U3A/U3B)lThe state variableslF1t+1=J1F1+K1F1= SRTF2F1+STPF2+F2F1lF1t+1(F2,F1,SRT,STP)=m(2,3,4,5,6,7,12,14)lF2T+1=J2F2+K2F2= SRTF2F1+STPF1

12、+F2F1lF2t+1(F2,F1,SRT,STP)=m(4,5,9,11,12,13,14,15)13 /40F2t F1tCRST00011110010000100001CENCLTCHl Clock enable : CEN =F2CEN =F2 F1F1 (U3D)l Reset enable : CRST =F2CRST =F2 F1F1 (U2A)l Latch enable : CLTCH =F2CLTCH =F2 F1F1 (U2B)14 /40l F1t+1(F2,F1,SRT,STP) =m(2,3,4,5,6,7,12,14)F2t F1t00011110SRT/STP0

13、00111100 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 0110010011001110l F2t+1(F2,F1,SRT,STP) =m(4,5,9,11,12,13,14,15)MSB=A ; LSB=D00011110SRT/STPF2t F1t000111100 1 3 2 MSB=A ; LSB=D4 5 7 6 12 13 15 14 8 9 11 10 011001110011001015 /40l F1t+1(F2,F1,SRT,STP)=m(2,3,4,5,6,7,12,14)l F2t+1(F2,F1,SRT,STP)=m(4,5,9,11

14、,12,13,14,15)MSB=A ; LSB=DMSB=A ; LSB=D00011110SRT/STPF2t F1t000111100 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 0110011100110010011001001100111016 /40l F1t+1(F2,F1,SRT,STP)=m(2,3,4,5,6,7,12,14)l F2t+1(F2,F1,SRT,STP)=m(4,5,9,11,12,13,14,15)MSB=A ; LSB=DMSB=A ; LSB=D00011110SRT/STPF2t F1t000111100 1 3 2 4

15、5 7 6 12 13 15 14 8 9 11 10 01100111001100100110010011001110F2t F1t00011110CRST010000100001CENCLTCHl Clock enable : CEN =F2CEN =F2 F1F1 (U3D)l Reset enable : CRST =F2CRST =F2 F1F1 (U2A)l Latch enable : CLTCH =F2CLTCH =F2 F1F1 (U2B)17 /40MSB=A ; LSB=D Transition tableMSB=A ; LSB=D00011110Next State,

16、SRT/STPF2t F1t0001111001100111001100100110010011001110CRST010000100001CENCLTCHPresent stateOutput variables18 /4010/00110/00100,0100/00000/00000,1001/10001/10011,1011,1011/01011/01000,0101,1100,1001,11CENCRSTCLTCHSRTSRTSRTSRTSRTSRTSTPSTPSTPSTPF2F1/CRST, CEN, CLTCHSRT,STPSRTSRTSTPSTPSTPSTP19 /40SRTSR

17、TD/A/C/B/STPSTPSRTSTPSRTSTPCRSTCENCLTCHA: No bullet passes over the start sensor.B: A bullet is passing over the start sensor.C: The bullet passed over the start sensor, and is on the itinerary between the start sensor and the stop sensor.D: The bullet is passing over the stop sensor.A: The bullet p

18、assed over the stop sensor and no bullet passes over the start sensor.20 /40cpcpDetermine flip-flop type: negative edge triggered J-K Determine circuit model: MooreDetermine variables1 input variable: X X1 output variable: Y Y1 1, Y, Y2 22 state variables: Y Y1 1 , , Y Y2 24 excitation variables: J

19、J1 1K K1 1, J, J2 2K K2 2J J1 1 =1 ; K=1 ; K1 1 =1 =1 J J2 2 = X= XY Y1 1 ; K; K2 2 = X = XY Y1 1Analysis example1J J1 1K K1 1Y Y1 1J J2 2K K2 2Y Y2 2=1=11 1X X21 /40 Next-state Truth TableInputInput Present Present statestateExcitationExcitationJ J2 2 K K2 2J J1 1 K K1 1Next Next statestateX XY Y2

20、2 Y Y1 1 Y Y2 2t+1 t+1 Y Y1 1t+1t+10 00 00 00 01 11 11 11 10 00 01 11 10 00 01 11 10 01 10 01 10 01 10 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 01 10 01 11 10 01 10 00 01 10 01 11 10 01 10 0J1 =1 K1 =1 J2 = XY1 K2 = XY1 Excitation equationAnalysis example10 1101001 22 /40Present Present

21、 statestateExcitationExcitationNext Next statestateY Yt t0 00 00 00 01 11 11 11 1J KJ K0 00 01 11 10 00 01 11 10 01 10 01 10 01 10 01 1Y Yt+1t+10 00 01 11 11 10 01 10 0Flip-flop Characteristic TableNext_state Truth Table0 00 00 00 01 11 11 11 10 00 01 11 10 00 01 11 10 01 10 01 10 01 10 01 11 11 11

22、11 11 11 11 11 11 11 11 11 11 11 11 11 10 01 10 01 11 10 01 10 00 01 10 01 11 10 01 10 0InputInput Present Present statestateExcitationExcitationJ J2 2 K K2 2J J1 1 K K1 1Next Next statestateX XY Y2 2 Y Y1 1 Y Y2 2t+1 t+1 Y Y1 1t+1t+11 10 01 10 01 10 01 10 00 01 11 10 01 10 00 01 1Analysis example12

23、3 /40Present Present statestateNext state/outputNext state/outputY Y2 2 Y Y1 1Y Y2 2t+1 t+1 Y Y1 1t+1t+10 00 01 11 10 01 10 01 11 10 01 10 00 01 11 10 0X =X = 0X = X = 11 10 01 10 01 10 00 01 1State TableY Y2 2Y Y1 1X X0 00 01 01 01 11 10 00 00 00 01 11 11 1 1 10 10 1State DiagramSynchronous Modulo-

24、4 up-down Synchronous Modulo-4 up-down countercounterAnalysis example124 /40Statement of the logic CircuitSynchronous Modulo-4 up-down counterSynchronous Modulo-4 up-down counterTiming DiagramNegative edge Negative edge trigger clocktrigger clockAnalysis example11 12 23 34 45 56 67 78 89 91 11 11 11

25、 10 00 00 00 00 0 0 01 11 1 0 0 0 0 0 0 1 1 1 1 0 00 01 10 01 1 0 0 1 10 01 1 0 00 00 00 01 10 00 00 01 10 0X XCPCPY Y2 2Y Y1 1Z Z25 /40Analysis example2lOutput equationlZ=XY2Y1 lExcitation equationlT2=(Y2Y1)(Y2Y1)X) =Y2Y1+(Y2Y1)XlT1=Y1XlFlip-flop characteristics equationlYt+1=YtTT2Y2Y2T1Y1Y1XZCPMea

26、ly 26 /40lNext-state equationlY1t+1=Y1T1=Y1Y1X=XlY2t+1=Y2T2=Y2(Y2Y1+(Y2Y1)X)lY2(Y2Y1+(Y2Y1)X)Analysis example2Present Present statestateNext state/outputNext state/outputY Y2 2 Y Y1 1Y Y2 2t+1 t+1 Y Y1 1t+1t+1/Z/Z0 00 01 11 10 01 10 01 10 00 00 00 00 00 00 01 1X =X = 0X = X = 1/0/0/0/0/0/0/0/01 11 1

27、1 11 10 01 10 01 1/0/0/0/0/1/1/0/00 0 11 0 0 1 10 0 00 1 1 1 10 1 01 0 1 0 10 0 11 0 0 1 127 /40l l“1101” sequence detector“1101” sequence detectorl lThe last bit “1” can overlap with the The last bit “1” can overlap with the next “1101” sequencenext “1101” sequenceAnalysis example2100011010/01/00/0

28、1/10/00/01/01/0DACB0/01/00/01/10/00/01/01/028 /40positive edge positive edge trigger clocktrigger clockAnalysis example21 12 23 34 45 56 67 78 89 91 11 11 10 01 11 10 01 10 0 1 11 11 1 0 0 1 1 1 1 0 0 1 1 0 00 01 11 11 1 0 0 1 11 10 0 0 00 00 00 00 00 00 00 0X XCPCPY Y2 2Y Y1 1Z Z1 11 11 11 11000110

29、10/01/00/01/10/00/01/01/0lZ=XY2Y1 29 /40Analysis example3lOutput equationlZ=Y2Y1lExcitation equationlD2=XY1lD1=X+Y2Y1lFlip-flop characteristics equationlYt+1=DD2Y2Y2D1Y1Y1XZCPMoore30 /40lNext-state equationlY2t+1=D2=XY1lY1t+1=D1=X+Y2Y1Analysis example3Present Present statestateNext stateNext stateY

30、Y2 2 Y Y1 1Y Y2 2t+1t+1Y Y1 1t+1t+10 00 01 11 10 01 10 01 10 01 10 00 00 01 10 01 1X=X=0X=X=11 11 11 11 10 00 00 00 0OutputOutputZ Z0 00 01 10 0lOutput equationlZ=Y2Y131 /40l l“ “100” sequence detector100” sequence detectorAnalysis example3D/1A/0C/0B/00 1 100011110/100/011/001/00 1 10001132 /40Analy

31、sis example31 12 23 34 45 56 67 78 89 91 11 10 00 00 01 10 00 01 1 0 00 01 1 1 1 0 0 0 0 1 1 1 1 0 01 11 11 10 0 0 0 1 11 10 0 1 10 00 00 01 10 00 00 0X XCPCPY Y2 2Y Y1 1Z Z1 110/100/011/001/00 1 100011lOutput equationlZ=Y2Y133 /40Asynchronous circuit analysisPay attention to Clock Pulse Pay attenti

32、on to Clock Pulse clock equations34 /40e.g.e.g.(1) circuit equations(1) circuit equations clock equations clock equationsoutput equationsdriving equations CPCP0 0=CP, =CP, CPCP1 1=Q=Q0 0 , (2) Characteristic equations(2) Characteristic equations(CP 0(CP 01) 1) ( (Q Q0 0 0 01) 1) 35 /40(3) State tabl

33、e(3) State table、state diagram and timingstate diagram and timing 1 0 / 10110 1 / 0010 0 / 00101 1 / 000CP1 CP0 36 /40(4) Logic function(4) Logic function Asynchronous M-4 down counterThe duty cycle ratio of Z is 25% and its period is 4*Tcp 37 /40Analyze the diagram and evaluate the design quality38 /40SolutionD4=Q4Q2+Q1D3=Q4D2=Q3D1=Q239 /40Conclusionsl4-bit flip-flops for Modulo-8 counterlAuto bootablel8 states are redundantl3-bit flip-flops enoughlQuality: Poor40 /40

展开阅读全文
相关资源
正为您匹配相似的精品文档
相关搜索

最新文档


当前位置:首页 > 高等教育 > 研究生课件

电脑版 |金锄头文库版权所有
经营许可证:蜀ICP备13022795号 | 川公网安备 51140202000112号