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1、Computer Organization & ArchitectureChapter 16Control Unit Operation16.1 Micro-Operations|A computer executes a program in many instruction cycles, typically, an instruction/cycleFetch/execute sub-cyclesEach sub-cycle has a number of steps|These steps are called micro-operations, see Fig.16.1|Each s
2、tep is simple and does very little, atomic operation of CPUSMicro-operations are the atomic operations of a processorConstituent Elements of Program Execution|Fetch CycleAccess PC, PC contains address of next instructionAddress moved to MARAddress placed on address busControl unit requests memory re
3、adResult placed on data bus, copied to MBR Then, to IRwMBR is now free for further data fetchesMeanwhile PC incremented by I(in parallel with data fetch from memory)|Fetch Sequence (symbolic)t1: MAR (PC)t2: MBR (memory) PC (PC) +It3:IR (MBR)(tx = time unit/clock cycle, a clock pulse)t1: MAR (PC)t2:
4、MBR (memory)t3: PC (PC) +I IR (MBR)Sequence of Events, Fetch Cycle1|Rules for Clock Cycle GroupingProper sequence must be followedMAR (PC) must precede MBR (memory)Conflicts must be avoidedCan not read & write same register at same timeMBR (memory) & IR (MBR) must not be in same cycleAlso: PC (PC) +
5、I involves additionUse ALUMay need additional micro-operations|Indirect Cyclet1: MAR (IRaddress) - address field of IRt2: MBR (memory)t3: IRaddress (MBRaddress)MBR contains an address for operandIR is now in same state as if direct addressing had been usedData Flow - Indirect Diagram|Interrupt Cycle
6、t1:MBR (PC)t2:MAR save-address PC routine-addresst3:memory (MBR)This is a minimumMay be additional micro-ops to get addressesNote, saving context is done by interrupt handler routine, not micro-ops|Execute CycleDifferent for each instructione.g. ADD R1,X add the contents of location X to Register 1
7、, result in R1t1:MAR (IRaddress)t2:MBR (memory)t3:R1 R1 + (MBR)|Execute Cycle (ISZ)ISZ X - increment and skip if zerot1:MAR (IRaddress)t2:MBR (memory)t3:MBR (MBR) + 1t4:memory (MBR) if (MBR) = 0 then PC (PC) + INotes:“if clause” is a single micro-operationMicro-operations done during t4|Executing Cy
8、cle (BSA)BSA X - Branch and save addressAddress of instruction following BSA is saved in XExecution continues from X+IUsed for Subroutine callt1: MAR (IRaddress) MBR (PC)t2: memory (MBR) PC (IRaddress)t3: PC (PC) + I|Instruction CycleEach phase of the instruction cycle can be decomposed into a seque
9、nce of elementary micro-operationsIn Fig.16.3, a new 2-bit register called the instruction cycle code (ICC) is assumedICC= 00: fetch01: indirect10: execute11: interrupt16.2 Control of The Processor|In order to describe the control unit, first, we must knowbasic elements of processormicro-operations
10、that processor performsfunctions that control unit must perform|Basic Elements of ProcessorALURegistersInternal data pathsExternal data pathsControl Unit|Types of Micro-operationData transferTransfer data between registersTransfer data from register to externalTransfer data from external to register
11、Perform arithmetic or logical ops|Functions of Control UnitSequencingThe control unit causes the processor to step through a series of micro-operations in the proper sequenceExecutionThe control unit causes each micro-operation to be performedThis is done by using Control Signals|Control Signals Con
12、trol signals - input ClockOne micro-instruction (or set of parallel micro-instructions) per clock pulseThis is sometimes referred to as the processor cycle time or the clock cycle timeInstruction registerOp-code of current instruction is used to determines which micro-instructions are performedFlags
13、Based on these flags, control unit determines state of CPU andResults of previous operationsControl signals from control busInterruptsAcknowledgements|Control Signals - outputControl signals to CPUCause data movement from one register to anotherActivate specific ALU functionsControl signals to contr
14、ol busControl signals to memoryControl signals to I/O modulesModel of Control Unit |Example of Control Signal Sequence - FetchMAR (PC)Control unit activates signal to open gates between PC and MAR, see fig.16.5, pp465MBR (memory) Simultaneously (t1,t2)t1:Open gates between MAR and address bus(c0)Mem
15、ory read control signal is on the control bust2:Open gates between data bus and MBR, data MBR (c5)Control makes PC add 1 and store the result back to PC (c3)|Another Control Signal ExampleFig.16.5 is a simple processor with an accumulatorWith each clock pulse, the control unit reads all of its input
16、s Clock InstructionFlagsControl busAnd emits a set of control signals to:Data paths : control internal flow of dataALU: control the operation of ALUControl busCauses micro-operations to occurTable 16.1 presents control signals needed by some micro-ops Data Paths and Control SignalMicro-operations an
17、d Control Signals|Several Conclusions on the Control UnitThe control unit is the engine that runs the entire computerIt controls everything with a few controlsSequencing micro-opsExecute some micro-ops|Internal Processor OrganizationIn CPU, Usually a single internal bus existsALU and registers are c
18、onnected, see fig.16.6Simplify interconnection & save spaceGates control movement of data onto and off the busControl signals control data transfer to and from external systems busTemporary registers may be needed for proper operation of ALU, except for ACInput register: YTemporary output register:
19、ZCPU withInternalBus16.3 Hardwired Implementation|Implementation of Control UnitImplementation methods of control unit can be classified into two categoriesHardwired implementationMicro-programmed implementationIn a hardwired implementation, the control unit is essentially a combinatorial circuitMic
20、ro-programmed implementation is the topic of Chapter 17|Control unit inputsFlags and control bus signalsEach bit means something, e.g. overflowInstruction registerOp-code causes different control signals for each different instructionUnique logic for each op-codeDecoder takes encoded input and produ
21、ces single output a decoder has n binary inputs and 2n outputs, each output actives a kind of controlsSee table 16.3Control Unit with Decoded Inputs|ClockRepetitive sequence of pulsesUseful for measuring duration of micro-opsMust be long enough to allow signal propagationDifferent control signals em
22、itted at different time within instruction cycleNeed a counter with different control signals for t1, t2 etc.|Control Unit LogicOutput control signal is a function of input control signalsSee Fig 16.10This function can be expressed by Boolean expressionBoolean expression is implemented in combinatio
23、nal circuitHardware circuit implementing the control unit is rather complexA simpler approach is micro-programming|Advantages with Hard Wired DesignsControl unit is viewed as a sequential logic circuit, used to generate fixed sequences of control signalsImplemented using any of a variety of “standar
24、d” digital logic techniquesPrincipal advantages:High(er) speed operationSuitable for smaller implementations Favored approach in RISC style designs|Problems With Hard Wired DesignsComplex sequencing & micro-operation logicDifficult to design and testInflexible designDifficult to add new instructions|Key pointsConcept of micro operationModel and organization of control unitImplementing modes of CU
