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1、1 018LG Process Introduction (1P6M)2Logic Circuit: 能够能够 展现展现 精确的模拟特性，精确的模拟特性，SOC与IC组成的系统相比，由于SOC能够综合并全盘考虑整个系统的各种情况，可以在同样的工艺技术条件下实现更高性能的系统指标若采用IS方法和0.35m工艺设计系统芯片，在相同的系统复杂度和处理速率下，能够相当于采用0.25 0.18m工艺制作的IC所实现的同样系统的性能与采用常规IC方法设计的芯片相比，采用SOC完成同样功能所需要的晶体管数目可以有数量级的降低ASIC: 为了满足消费者特定需求而专门设计的半导体为了满足消费者特定需求而专门设计
2、的半导体电路电路3VDDINOUTCMOS反相器反相器VDDYA1A2与非门：与非门：Y=A1A24基本电路结构：基本电路结构：MOS器件结构器件结构基本电路结构：基本电路结构：CMOS518LG adopt 27 Photo mask , if include ESD layerAA/Poly/CT/ M1M5/ V1V5 use DUV scanner (13 layer) “ DARC” Cap on Critical layer and Top M6 Poly & M1M5 adopt OPC (optical proximity correction) for line-end sh
3、orting & island missingComposite Spacer (ONO) PSM method apply on CT layer Cobalt salicide processLow K IMD layer (FSG)0.18umProcessFeatures6OutlineOutline1. STI/Trench Isolation 2. Well Definition/Vt Adjust 3. Gate Formation4. N/PMOS Formation 5. Salicide Formation6. ILD Layer / Contact CT (FEOL: d
4、evice)7. Metal / VIA 8. Top Meta l Via9. Passivation (BEOL: interconnect)7WAFERSTART&RSCHECKP type 8 12 ohm-cm, non-EPI wafer StartOX100A dry 1. PR isolation 2. Prevent the laser mark Si recast 3. Surface cleanness 4. Backside oxidation & trap the metal ionZEROPhoto For ASML stepper system global Wa
5、fer alignmentZEROFullydryetch(OX100A+SI1200+-200A)ZEROStrip1625 Nitride 110 PAD OxideWaferMark(ForWaferalignment)ScrubberClean(TJBB)StartoxideRMNLH320A(50:1HF350sec)Meas:OxRMTHK(2535A)AAOXPre-cln NCR1DH75ARCAMPadoxide 110+-7A/ 920oC dry O2As buffer layer to release stress, due to SIN and Si differen
6、t lattice constantNitrideDEP(w/Iscrubber)1625+- 100A / 760oCWafer StartWafer StartSTOP LAYER of STI CMP 8SiONDEP(CVD)FE DARC320 (w/Iscrubber)AAPhoto(120layer)AAEtch(5800A)SiN/Ox+Si etch ( 80 +-2degree) AAAsherMattson ( Rcp: 1 )Polymer&WetStripNDH15APRRMSC1M ( 100:1 HF 30sec)AA THK STI-PO PAD (5400+-
7、160 A)16250 Nitride110 PAD OxideAEI = 0.25+-0.02ADI = 0.23+-0.02STI ETCH ToreduceSINreflectionandimprovePRresolutionasanARClayer9STIPadOXPreClnNCR1DH75ARCAM(100:1HF180sec)STILinerOX 1000C,DRYOX(200+-12A)Anneal(Diff)1100C,2hrs(Furnaceann.)HDPFillHDPCVDOX5.8KAW/OARsputterRTAPRECLNNRCAM(SC1+SC2)HDPCVDO
8、XRTA1000RTA020S(1000C,20sec,N2)5800 HDP1625 Nitride110 PAD OxideHDP DepositionTobettershallowtrenchfillingFordamagereductionbyHDPandHDPoxdensification10P SubstratePad oxideP SubstrateAA SiNAA Reverse AARPhoto(121layer)AAR= (AA-0.4)+0.4) -0.2AAREtchStoponSiNAARAsherMattson(Rcp:1)AARwetstripNPRRM(SPMo
9、nly)Pad oxideP SubstrateAA SiN1.Bettersurfaceflatness2.ImprovedthroughputbyOXremoving11STIPre-CMPTHK-POPAD(6100+-225A)STIPolish&in-situCln(STI_XXXX)?CMP是磨到是磨到NIT上。上。STIPre-CMPTHK-POPAD(3600+-250A),SIN(1050+-50)AANITRMNLH90AHPO2450A(50:1 HF + H3PO4)THIN OXIDE THK-P PAD ( 82+-17) STIPADOXRMNLH60A(50:1
10、 HF 65 sec) SACOXPRECLNNCR1DH100ARCAM(100:1HF240sec)SACOX110+-7A/ 920oC 45min dry O2 As implant screen oxide STI CMP & NIT RM110 SAC Oxide12N_WellPhoto(192layer)Implant:NWELLIMPP440K15E3T00WELL IMP注入的位置最深，用以调节井的浓度防止Latch-up效应。PCHANNELIMPP140K50E2T00 CHANNEL IMP位置较浅，加大LDD之下部位的WELL浓度，使器件工作时该位置的耗尽层更窄，防
11、止器件PUNCH THROUGH。VTPIMPA130K90E2T00VT注入，靠近器件表面，调节器件的开启电压NWELLAsherMattson:21NWELLWetStripSPMonlyNWELLAnnealPreclnMRCAM(SC1+SC2)IMPLANTDAMAGEANNEAL1000RTA010S(1000C;10secN2(PVD)N-WellP-WellP-VTP-pthruN-Well and Vt_P adjustment13P_WellPhoto(191layer)Implant:PWELLIMPB160K15E3T00NCHANNELIMPB025K44E2T00N
12、_VTIMPD170K70E2T00PWELLAsherMattson:21PWELLWetStripSPMonlyP WELL N pthruN_VTP-Well and Vt_N adjustment1450 thick gate oxide32 thin gate oxide2000A polyFinal 70 AThick/ Thin Gate oxide defineSACOXRMNLH60A(50:1HF65sec)SACOXTHK-POPAD(3200+-400A)GATE1_OXPreClnNCR1DH100ARCAMGATE1_OX800C,48A+-4A,wetDualGA
13、TEPhoto(131layer)(0.45+/-0.05um)GATE1ETCHN(NLB75A)GATE1StripSPMonlySTITHK-POPAD(3150+-180A)GATE2_OXPreClnNCRRCAMGATE2OX 750C,27+-2A,wetThingateThickgate15POLYDEPOSITIONPOLY2000A,620CSiONDEPFEDARC320POLYPHOTO(130layer)PolyARCetch+PolyetchGATEAsherMattson(Rcp:1)GATEWetStripNDH5APRRM(100:1HF10sec+SPM)T
14、HICKGATEOXIDETHK-PPAD(25+-5A)SIONRMNLH5AHP0550A50:1HF+H3PO4GATERE-OxidationPreClnNRCA(SC1+SC2)PolyRe_Oxidation1015C,21ARTO(T 1C,THK 0.8 A )N-WellP-WellADI 0.18+-0.015umAEI 0.18+-0.015umPoly Gate Definitiona.Recover ETCH damage to GOX.b. Prevent native-oxide For thermal budget&good oxide profile arou
15、nd poly gate16NLDD1Photo(116layer)Implant:NPocketimplant(D130K25E3T30R445)NLDDimplant(A003K80E4T00)NLDD1Asher&WetStrip(21+SPM)PLDD1Photo(113layer)Implant:PPocketimplant:(A130K30E3T30R445)PLDDimplant(F005K20E4T00)PLDD1Asher&WetStrip(21+SPM)N-WellP-WellNNPPLDD1 Definition (Core device, 1.8V)NLDD 114 m
16、ask PLDD 113 mask PLDD IMPNLDD IMPHotcarriereffect17LDD2 Definition ( I/O device, 3.3 V)N-WellP-WellNNPPPLDD IMPNLDD 116 mask PLDD 115 mask NLDD IMPPLDD2(115layer)PLDD2PhotoPLDD2implant(F040K30E3T00)PLDD2Asher&WetStrip(21+SPM)PLDD2-RTA0950RTA010S(950C,10sec)NLDD2(114layer)NLDD2PhotoNLDD2implant(P040
17、K40E3T00)NLDD2Asher&WetStrip(21+SPM)18Nitride SpacerN-WellP-WellNNPPSPADep.PreclnNRCA(SC1+SC2)LININGTEOSDiff680C,150+-20ASiNSpacerDiff650C,300+-30AOXSpacerIMP680C,TEOS1000+-25ASPACERETCH(Oxide+SIN)PostCleanNCR(SPMonly)SPAPOSTTHKTRENCHOX(3100+-480,Avg.=3280A),THINOX(175+-20A)OxideStripNDH25A(100:1HF6
18、0sec)SPAPOSTOXSTRIPN-PAD(045,AVG=10A)Composite Spacer ONO,liningTEOS-SIN-TEOS19N+N+Photo (198layer)N+implant1(A060K51E5T00)N+implant2(P035K15E4T00)Asher&WetStrip(22+SPM&APM)N+Anneal1025RTA020S(1025C,20sN2)P+P+Photo (197layer)P+Implant1(B005K33E5T00)P+Implant2(B015K30E3T00)Asher&WetStrip(22+SPM&APM)N
19、-WellP-WellP+N+N+P+NP & PP DefinitionNSD 198 mask PSD 197 mask NSD IMPPSD IMP Two times SN+/SP+ IMP, to reduce concentration between S/D and WELL to optimize leakage. Highdoseimp.willcausePRresiduemoreeasily20ESD ESDPHOTO(72HRQTIMEtoP+IMP1),110layerESDOVERLAYESDCD-PHESDADIYEDEFECTINSPECTIONYEDEFECTI
20、NSPECTIONESDIMP(B050K25E3T00)ESDASHERESDWETSTRIP(NPRRM)ESDASI21ESD Backup SlipESD: ElectroStatic Discharge. Electron will generate in ESD: ElectroStatic Discharge. Electron will generate in Process and damage circuit by discharging with High Voltage Process and damage circuit by discharging with Hig
21、h Voltage and High current. and High current. 22Pre-clnNRCAM(100:1HF60sec)SABCapOxSRO350AP+RTAAnnealingPVD1015RTA010S(1015C,10sec)PostP+RTATHK-POPAD(3400+-400,Avg.=3470A)SABPhoto(155layer)SalicideBlockEtchDry+WETETCHSABAsher+wetstrip(32+SPM&APM)SABTHKTRENCHOX-POPAD(3100+-400,Avg.=3000A)N-WellP-WellS
22、al Blk PE TEOSP+P+N+N+Salicide Block23Pre-COoxideRMNDH25A(100:1HF60sec)ChangeCoPod&CassetteSalicideDeposition(E30C85N20)(Ar sputter 30A/Co 85A/TiN 200A) Salicide1stRTA(530oC 30sec N2 ) N-WellP-WellCO SailcideP+P+N+N+SalicideSelectiveEtchNSC1M2SC1NH4OH:H2O2:H2O1:1:5M2H3PO4:HNO3:CH3COOH 70:02:12Salici
23、de2ndRTA (850oC 30sec N2 ) Co Salicide Ar sputter 30A will etch nature oxide 30A ; 24PE-SION400ADEPCVDHKSION400highkmaterialChangeBEOLPod&CassetteILDBPTEOSDepositionCVD31B65P2K480CBPTEOSFLOWIMP650C,N2,30minCRCleanNCR(SPMonly)PETEOSdepositionCVD10.5KILDPRE-CMPTHK-PPAD(12500+-900,Avg.=12350A)OxCMPforI
24、LD7.5KILDPOST-CMPTHK-PPAD(7500+-600,Avg.=7560A)ILDCRCleanNCR(SPMonly)N-WellP-WellP+P+N+N+2 k SABPSG10.5k PETEOS400 SION ILD Deposition25CTDARCCVD(SiON/OX-200A/600A)ScrubberCTPhoto(156layer)ADI CD 0.255+/-0.02um AEI CD 0.225+/-0.025umCTetchCTAsher41ChangeCoPod&CassetteCTwetstrip(sendtoFAB1Backup)NPRR
25、MSC1MChangeBEOLPod&CassetteN-WellP-WellP+P+N+N+ Contact 26CONTGLUELAYERPVDETCH100A/IMPTI200A/CVD-TIN50ASilicideannealing(690C,N260s)3.3kWCVDDEPWCMPWTi/TiNN-WellP-WellP+P+N+N+W-Plug27MET1GLUE(200Ti/250TiN)MET1Acu(4000AlCu/50Ti/300TiN)ScrubberInorganicBARC320AScrubberM1Photo(160layer)ADI CD 0.22+/-0.0
26、15um AEI CD 0.24+/-0.02umM1etchM1wetstripEKCPureH2AlloyPVD(410C,90sec)Metal 1 N-WellP-WellP+P+N+N+Met 128SROLinerDep.CVDSiliconRichOxideHDP6KCVDPE-FSGDep.11.5KCVD(Fluorinated Silicate Glass),IMD1CMPIn-situPE-N2treatment&USGCap2K(Undoped Silicate Glass),1.CoverFSGlayer2.PreventF-diffusive.3Topreventm
27、etalavoidOx CMP for IMDIMD1 ( SiON/OX- 600A + 200A )Via1 Photo (178layer) ADI CD 0.285+/-0.02um AEI CD 0.275+/-0.025umVia 1 etch Via 1 Asher & Wet strip (41 + NEKC30)Met 1N-WellP-WellP+P+N+N+6k HDP11.5 k PETEOSIMD 1 & Via 1Met 1N-WellP-WellP+P+N+N+29VacuumBake(300C)VIAGLUELAYERETCH130/160Ti/70TiN(IM
28、P/CVD)3.3kWInter-metalDep.(M2M5)ScrubberSION320Dep.ScrubberInter-metalPho(M2M5,180-184)ADI CD 0.26+/-0.02umAEI CD 0.28+/-0.025umInter-metalEtch(M2M5)WetstripMet 1N-WellP-WellP+P+N+N+160 Ti / 70 TiNInter-metal Met 1N-WellP-WellP+P+N+N+Met 2Met 3Met 4Met 530IMD2IMD5SROLinerDep.HDP6KCVD(Goodfillingcapa
29、bility，slowgrowthrateandhighcost)PE-FSGDep.11.5KCVD(Cheapandhighgrowthrate）IMDx(x=25)CMPIn-situPE-N2treatment&USGCap2K(IMD5Cap3.5K)Ox CMP for IMDIMDx(x=25)( SiON/OX- 600A + 200A )Via x(x=24) Photo (175-179) ADI CD 0.285+/-0.02um AEI CD 0.275+/-0.025umVia x(x=24) etch Via x(x=24) Asher & Wet strip (4
30、1 + NEKC30)Met 1N-WellP-WellP+P+N+N+Met 231SROLinerDep.PE-FSGDep.11.5KIn-situPE-N2treatment&USGCap3.5KSurfacenitrigenationIMD5CMPIMD5ARC(SiON/OX-600A+200)Via5PhotoADI CD 0.4+/-0.04umVia5etchAEI CD 0.39+/-0.04umVia5Asher&Wetstrip (41+NEKC30)Via5WDep.4000AWC5W_CMPMET6GLUE(200Ti/250TiN)MET6AlCu(8000AlC
31、u/375TiN).M6PhotoADI CD 0.49+/-0.045um(line)M6etchAEI CD 0.51+/-0.05umM6wetstripN-WellP-WellP+P+N+N+Met 1Met 2Met 3Met 4Met 5Met 6Top Via & Top Metal 3210kHDPoxidedepPE-SION1.5KDEPCVDPE-SIN6KDEPCVDPDPhotoforbondpadHDPpassivationetchResistStripAlloy-410C,30PVDN-WellP-WellP+P+N+N+Met 1Met 2Met 3Met 4M
32、et 5Met 61.5kSION+6kA SIN10k HDPPassivation 33Q & AThanks341為何需要為何需要StartOxide?AnsForzerolayerPHOprocess,beforePHOPRdeposition,thereneedbufferoxidetoisolatePRmaterialontouchwithSi.ZerolayerisdesignedbyASMLsteppersystem.PreventthelasermarkSirecastbeingre-depositedontoSisurfacedirectly,becauseSiishydr
33、ophobiclikeandthesere-depo.Particleisveryhardtoberinseoff.AsthefirstHIGHtemperaturecycleforH-L-Hdenudedzone(oxygenfreetreatment).Pre-setthesurfacecleannessconditionrightafterFabreceivedthenewwafermaterials.ZERO-STARTWAFERSTART(PTYPE、8-12OHM/SQ)START-OXBCLN1(22220A)SPM60/HF180/APM420/HPM180/HF0START-
34、OXSTARTOX(1100C；350A)ZERO-PHOZEROPHOTO(ALIGNMENTMASKAT55DEG)ZERO-ETCHZEROFULLYDRYETCH(OX350A+SI1200A)ZERO-ETCHRESISTSTRIPPING(PSC)PARTIALSTRIPZERO-ETCHPRCAROSSTRIP(ETCH)SPM+APM由上表可以很明顯地看出StartOX的第一個功用，就是不希望為有機成分(C-Hbond)的光阻直接碰觸到矽晶圓表面。在電子級的矽晶圓中，氧及碳雜質是無法完全被移除的，一般的含量約為1016cm-3左右。除以固溶態(Solidsolution)存在外
35、，也會以微析出物(Micro-precipitates)的形式存在於矽晶圓中。這些絕緣的微析出物將會引致在空乏區(Depletionregion)的電力場(Fieldline)彎曲，而造成局部的電場梯度(Fieldgradient)變大，因此在較低的電壓就有可能造成接面崩潰(Junctionbreakdown)。另一方面碳氧雜質無論是以插入(Interstitial)或替代(Substitutional)的方式固溶於矽晶圓中也容易變成佈植雜質(Dopant)或缺陷集中的中心。StartOX的另一個用途則是在WAFERSTART刻雷射刻號時高功率雷射入射矽晶圓表面引致的融渣會在STARTOXRE
36、MOVE後被移除，不過FAB5目前是使用Soft-laser來作刻號，並不會有這個問問題。另外wafer中总会含有metalion,在wafer背面掺入oxygen,hightemperatureprocesstheoxygeninthewafercantrapthemetalion.AnsZerolayer352為何需要為何需要Zerolayer?LaserMark?ASMLsteppersystemrequiresazeromarkforglobalalignmentpurpose.ForASML300Btheoverlayspecforsinglemachineis45nm,format
37、ed300Bmachine75nmandfor300to200machine95nm.TheoverlayperformanceisthebasiccharacteristicofstateofartStepper.UsezerolayerglobalalignmentmarksystemcanhelptoimprovetheOVLperformance.(OVL156_120)2=(OVL156_0)2+(OVL120_0)2LasermarkWaferidentification(includeLotid,waferID)Laser-mark是wafer在FAB內身份證明，由11碼組成：例
38、如：F12345-01XX前6碼代表LotID第7碼為-第8,9碼為WaferID(0125)第10,11碼為序號SMICreferncetoLotIDnamingruleandlottypenamingruleAnsZerolayer363738v定义定义:Latchup是指是指cmos晶片中晶片中,在电源在电源powerVDD和地线和地线GND(VSS)之间由于寄生的之间由于寄生的PNP和和NPN双极性双极性BJT相互影响而产生的一低阻抗通路相互影响而产生的一低阻抗通路,它的存在会使它的存在会使VDD和和GND之间产生大电流之间产生大电流. (. (Photoelectron or ion
39、izing from circumstance will induce leakage current in WELL-SUB junction. ) )-Latchup产生的过度电流量可能会使芯片产生永久性的破坏产生的过度电流量可能会使芯片产生永久性的破坏,Latchup的防范的防范是是ICLayout的最重要措施之一的最重要措施之一-随着随着IC制造工艺的发展制造工艺的发展,封装密度和集成度越来越高封装密度和集成度越来越高,产生产生Latchup的可能性会的可能性会越来越大越来越大p-subn-wellVss (gnd)VddVoutVinRwRsubP+P+P+n+n+n+ssddTak
40、ing N-WELL CMOS device as an example, its 4 terminals (P+,N-WELL, P-SUB,N+) will form a parasitic circuit which include 2 coupling bipolar device.39工艺级抗闩锁措施：工艺级抗闩锁措施：(1) (1) 降低少数载流子的寿命可以减少寄生双极型晶体管的电流增益，一般使降低少数载流子的寿命可以减少寄生双极型晶体管的电流增益，一般使用金掺杂或中子辐射技术，但此方法不易控制且也会导致漏电流的增加。用金掺杂或中子辐射技术，但此方法不易控制且也会导致漏电流的增加。
41、(2) (2) 后退阱技术，可以减小寄生三极管的阱电阻，防止寄生三极管后退阱技术，可以减小寄生三极管的阱电阻，防止寄生三极管EBEB结导通。结导通。(3) (3) 另一种减少闩锁效应的方法，是将器件制作于重掺杂衬底上的低掺杂外另一种减少闩锁效应的方法，是将器件制作于重掺杂衬底上的低掺杂外延层中。重掺杂衬底提供一个收集电流的高传导路径，降低了延层中。重掺杂衬底提供一个收集电流的高传导路径，降低了RSRS，若在阱中加入重，若在阱中加入重掺杂的掺杂的p+p+埋层埋层( (或倒转阱或倒转阱) )，又可降低，又可降低RWRW。实验证明。实验证明, ,此方法制造的此方法制造的CMOSCMOS电路有很高电路
42、有很高的抗闩锁能力。的抗闩锁能力。(4) (4) 闩锁亦可通过沟槽隔离结构来加以避开。在此技术中，利用非等向反应闩锁亦可通过沟槽隔离结构来加以避开。在此技术中，利用非等向反应离子溅射刻蚀，刻蚀出一个比阱还要深的隔离沟槽。接着在沟槽的底部和侧壁上生离子溅射刻蚀，刻蚀出一个比阱还要深的隔离沟槽。接着在沟槽的底部和侧壁上生长一热氧化层，然后淀积多晶硅或二氧化硅，以将沟槽填满。因为长一热氧化层，然后淀积多晶硅或二氧化硅，以将沟槽填满。因为n n沟道与沟道与p p沟道沟道MOSFETMOSFET被沟槽所隔开，所以此种方法可以消除闩锁。被沟槽所隔开，所以此种方法可以消除闩锁。（5 5）以上措施都是对传统）
43、以上措施都是对传统CMOSCMOS工艺技术的改造，更先进的工艺工艺技术的改造，更先进的工艺SOI(Silicon on SOI(Silicon on Insulator)Insulator)等能从根本上来消除闩锁产生，但工艺技术相对来讲要复杂一些。等能从根本上来消除闩锁产生，但工艺技术相对来讲要复杂一些。 4015、什么是、什么是PUNCH THROUGH，为消除它有哪些手段？，为消除它有哪些手段？PUNCH THROUGH是指器件的S、D因为耗尽区相接而发生的穿通现象。S、D对于SUB有各自的耗尽区。当器件尺寸较小时，只要二者对衬底的偏压条件满足，就可能发生PUNCH THROUGH效应。这
44、样，不论GATE有无开启都会有PUNCH THROUGH产生的电流流过S、D。极大的降低电子产品的功耗在制程中，采用POCKET和CHANNEL IMP来加大容易发生加大容易发生PUNCH THROUGH位位置的置的SUB浓度，浓度，从而减小器件工作时在该处产生的耗尽层宽度以达到避免PUNCH THROUGH发生的效果。 (耗尽层的宽度与掺杂浓度的平方成反比，)411、字体安装与、字体安装与设置置如果您对PPT模板中的字体风格不满意，可进行批量替换，一次性更改各页面字体。1.在“开始”选项卡中，点击“替换”按钮右侧箭头，选择“替换字体”。（如下图）2.在图“替换”下拉列表中选择要更改字体。（如下图）3.在“替换为”下拉列表中选择替换字体。4.点击“替换”按钮，完成。412、替、替换模板中的模板中的图片片模板中的图片展示页面，您可以根据需要替换这些图片，下面介绍两种替换方法。方法一：更改图片方法一：更改图片1.选中模版中的图片（有些图片与其他对象进行了组合，选择时一定要选中图片本身，而不是组合）。2.单击鼠标右键，选择“更改图片”，选择要替换的图片。（如下图）注意：注意：为防止替换图片发生变形，请使用与原图长宽比例相同的图片。4142赠送精美图标
