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1、IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 53, NO. 10, OCTOBER 20062187Design on Power-Rail ESD Clamp Circuit for 3.3-VI/O Interface by Using Only 1-V/2.5-V Low-VoltageDevices in a 130-nm CMOS ProcessMing-Dou Ker, Senior Member, IEEE, Wen-Yi Chen, and Kuo-Chun Hsu, Member, IEEE
2、AbstractAnewp o w er- rai l el ectro stati cdi sch arg e( E S D) cl ampci rcu i t f o r ap p l i cati o n i n 3 . 3 - Vmi xed- v o l tag e i np u to u tp u t ( I/ O)i nterf ace i s p ro p o sed and v eri ?ed i n a 1 3 0 - nm 1 - V / 2 . 5 - VC MOSp ro cess. Th e dev i ces i n th i s p o w er- rai l
3、E S Dcl ampci rcu i t are al l1 - Vo r2 . 5 - Vl o w - v o l tag enMOS / p MOSdev i ces, w h i charesp eci al l ydesi g ned w i th o u t su f f eri ngth e g ate- o xi de rel i abi l i tyi ssu e u nder3 . 3 - VI/ Oi nterf ace ap p l i cati o ns. A sp eci al E S Ddetecti o n ci rcu i treal i z ed w i
4、thth e l o w - v o l tag e dev i ces i s desi g ned and added i n th ep o w er- rai l E S Dcl ampci rcu i t toi mp ro v e E S Dro bu stness o f E S Dcl ampdev i ces by su bstrate- tri g g ered tech ni q u e. Th e exp eri mentalresu l ts v eri ?ed i n a 1 3 0 - nm C MOSp ro cess h av e p ro v en th e
5、 excel -l ent ef f ecti v eness o f th i s newp ro p o sed p o w er- rai l E S Dcl ampci r-cu i t.Index TermsE l ectro stati c di sch arg e ( E S D) ,E S D p ro tecti o nci rcu i t,h i g h - v o l tag e to l erant,p o w er- rai lE S D cl amp ci rcu i t,su bstrate- tri g g ered tech ni q u e.I. INTRO
6、DUCTIONELECTROSTATIC (ESD) has been an important reliabilityissue for modern integrated circuit (IC) products in thescaled-down CMOS technologies. Since the stored electrostaticet al.: DESIGN ON POWER-RAIL ESD CLAMP CIRCUIT FOR 3.3-V I/O INTERFACE2189Fig. 2. New proposed power-rail ESD clamp circuit
7、 with only 1-V and 2.5-Vdevices for operating under high-voltageVh of 3.3 V.0.8A (8A), which could be still too large for most portablemicroelectronic products and low-power IC products.Another well-known and widely used high-voltage-tolerantstructure is the stacked-nMOS configuration 8, where the t
8、opgate of the stacked nMOS is biased at a relatively low voltage todrop the drain voltage of the bottom nMOS and to safely meetthe reliability limitation during normal circuit operating condi-tions. Unfortunately, the stacked nMOS has been found to havesome disadvantages of ESD protection capability
9、, includingthe nonuniform turn-on behaviors, slower turn-on speed, andthe lower ESD robustness. Therefore, to uniformly and quicklyturn on the stacked nMOS in the mixed-voltage I/O buffersunder ESD stress conditions, some ESD detection circuits aretherefore developed to trigger the stacked nMOS 26,
10、27. Inthis work, a novel low-leakage power-rail ESD clamp circuit,which contains a high-voltage tolerant ESD detection circuit tosubstantially increase the ESD protection efficiency of stackednMOS, is proposed.III. NOVELPOWER-RAILESD CLAMPCIRCUIT FORHIGH-VOLTAGEAPPLICATIONSThe novel power-rail ESD c
11、lamp circuit which contains ESDclamp device and ESD detection circuit is shown in Fig. 2,where the ESD clamp device is realized by a substrate-trig-gered stacked nMOS (STnMOS). The new proposed power-rail ESD clamp circuit is realized with only 1-V and 2.5-Vdevices to operate at 3.3-V I/O interface
12、without the risk ofgate oxide reliability. Under normal circuit operating condi-tions, the ESD detection circuit is inactive and doesnt inter-fere with the functions of internal circuits. But, it is active toprovide the substrate-triggered current to quickly trigger on theSTnMOS device under ESD str
13、ess conditions. The STnMOS isformed by two stacked nMOS transistors with 2.5-V gate oxidein the 130-nm 1-V/2.5-V CMOS process. The gate of the topnMOS transistor of STnMOS is biased atl of 1 V througha resistor, and that of the bottom nMOS transistor is directlyTABLE IDEVICEDIMENSIONS OFESD PROTECTI
14、ONCIRCUIT INTHISWORKconnected to. The voltage level at the shareddiffu-sion region between the top and bottom nMOS transistors ofSTnMOS device will be kept at-during normal circuitoperating conditions, whereis the threshold voltage of the2.5-V nMOS transistor. Therefore, the STnMOS is free fromthega
15、te-oxide reliability issueunder high power-supply voltageh of 3.3 V. The ESD detection circuit is formed by Mp1,Mp2,andC of2.5-VpMOSdevices,Mn1of1-VnMOSdevice,Mn2 of 2.5-V nMOS device, and an n-well resistor R1. The se-lected device dimensions of the proposed ESD detection circuitin this work is lis
16、ted in Table I.A. Circuit Operation Under Normal Power-On TransitionWhen the 3.3-Vh and 1-Vl have been poweredon, the gate of Mp1 (node 1 in Fig. 2) is biased at 3.3 V throughthe resistorR1, and the gate of Mp2 is biased at 1 V through theresistorR2 of 1 k. With a gate-to-source bias of 0 V, the Mp1
17、should be kept off. With a gate-to-source bias of 1 V, the Mn1is turned on. So, no trigger current will be generated from theESD detection circuit into the trigger node (node 3 in Fig. 2) ofthe STnMOS. The turned-on Mn1 can guarantee the off-state ofSTnMOS during normal circuit operating conditions.
18、 Becausethe gate of Mp2 is biased atl through the resistorR2, thedrain voltage of Mp1 (node 2 in Fig. 2) is kept atV,whereisthethresholdvoltageofthe2.5-VpMOStransistor.By such arrangement, all low-voltage devices in the new pro-posedpower-railESDclampcircuitarefreefromthegate-oxidereliability issue
19、under normal circuit operating conditions withh of 3.3 V in the mixed-voltage I/O interfaces. Fig. 3(a)shows the Hspice-simulated voltages on nodes of the ESD de-tection circuit. In this simulation, theh andl are, re-spectively,powered-onto3.3Vand1Vwithasimultaneousrisetime of 1 ms. The Hspice-simul
20、ated results show that the volt-ages across the gate drain, gatesource, and gatebulk termi-nals of every device do not exceed the process limitation. More-over,thegatevoltageofpMOSMp1intheESDdetectioncircuitwith the selected R1-C value can follow up the power-on tran-sition ofh to turn off the pMOS
21、Mp1.B. Circuit Operation Under ESD TransitionWhenESDtransientvoltageisappliedtohwithrel-atively grounded, the gate of Mp1 (node 1 in Fig. 2) is initiallykept at a low voltage level (around 0 V) due to the RC delay ofR1 and C in the ESD detection circuit. Thel node is ini-tiallyfloatingwithaninitial
22、voltagelevelof0V,beforetheESDAuthorized licensed use limited to: Zhejiang University. Downloaded on December 9, 2008 at 10:17 from IEEE Xplore. Restrictions apply.I: REGULAR PAPERS, VOL. 53, NO. 10, OCTOBER 2006Fig. 3. Hspice simulation on the new proposed ESD detection circuit under (a)normal power
23、-on transition with a rise time of 1 ms and (b) 0-to-7 V ESD-liketransition with a rise time of 10 ns.voltage is applied acrossh and. Some ESD transientvoltage would be coupled tol through the parasitic capac-itance when ESD stress is zapped onh, but the R2 and theparasitic capacitance at the gates
24、of Mn1 and Mp2 will keep thegate of Mp2 at 0 V for a long time period. So, Mp1 and Mp2with initial gate voltages atV can be quickly turned on bythe ESD energy to generate the trigger current into the triggernode (node 3 in Fig. 2) of STnMOS. As long as the base-emittervoltage of the lateral n-p-n BJ
25、T inherent in the STnMOS deviceis greater than its cut-in voltage ofV, the STnMOS can betriggered on to discharge ESD current fromh to grounded. Fig. 3(b) shows the Hspice-simulated voltages and currentof the ESD detection circuit under ESD transition. A 0-to-7 VESD-like voltage pulse with rise time
26、 of 10 ns is applied to theh to simulate the ESD transition before junction break-down on the devices. The Hspice-simulated results show thatthe gate voltage of Mp1 is kept low due to the time delay of R1andC. The pMOS Mp1 and Mp2 can provide the substrate-trig-gered current larger than 60 mA within
27、 10 ns when the 0-to-7 Vtransient voltage is applied toh. Simulation on the voltageof node 3 in Fig. 3(b) also verifies that the substrate bias can beachieved by the substrate-triggered current generated from theproposed ESD detection circuit. By selecting the device dimen-sions, the substrate-trigg
28、ered current can be designed to meetdifferent applications or specifications. The time constant of R1and C should be designed around the order ofs to distin-guish the power-on transition (with a rise time of several mil-liseconds) from the ESD transition (with a rise time of severalnanoseconds) 4.If
29、Mn1isturnedonduringESDtransitionbyunexpectedcou-pling effect to its gate through the parasitic capacitance in thelayout, the base voltage of the lateral BJT could be pulled downto zero to turn off the lateral BJT in the STnMOS device. Toavoid such possible condition during ESD transition, the Mn2is
30、added in the ESD detection circuit to keep the gate of Mn1and Mp2 at 0 V, when the base voltage of lateral BJT in theSTnMOS device is charged up by the current flowing throughMp1 and Mp2.IV. EXPERIMENTALRESULTSThe proposed power-rail ESD clamp circuit has been de-signed and fabricated in a 130-nm 1-
31、V/2.5-V CMOS process.The stand-alone STnMOS with the same device dimensionand layout has been also fabricated in the same chip forreference. In the test structures, all the STnMOS devices aresalicide-blockedwhereasalltheESDdetectioncircuitsarefullysalicided. The stand-alone 2.5-V STnMOS has a bipola
32、r triggervoltage () of 11.7 V and a holding voltage larger than thehigh power-supply voltage (3.3 V). Therefore, the stand-aloneSTnMOS is not a good power-rail ESD clamp device due to itshigh bipolar trigger voltage. In this section, the experimentalresults will show that the new proposed ESD detect
33、ion circuitcan effectively lower theand substantially increase theESD robustness of STnMOS. Moreover, the experimentalresults also show that the proposed ESD detection circuit cansuccessfully distinguish the normal power-on transition andthe ESD transition. Therefore, ICs with the new proposedhigh-v
34、oltage-tolerant power-rail ESD clamp circuit have norisk of latch-up issue.A. Standby Leakage CurrentTo save the power consumption of portable devices or low-power applications, especially chips that are driven by smallbatteries, the standby leakage current becomes one of majorconcerns 11, 12. The m
35、easured leakage currents of the fab-ricated power-rail ESD clamp circuit under different tempera-tures are shown in Fig. 4, where the STnMOS is drawn witha device dimension (W/L) ofmm. With a leakagecurrentofnAunderthetemperatureof125 C,leakagecur-rent of the new proposed power-rail ESD clamp circui
36、t is quitesmall as comparing to those of the prior arts. Table II summa-rizes the comparison on the leakage current between the newproposed power-rail ESD clamp circuit and the prior arts 10,25. In 22, diode strings were fabricated on p-substrate withepitaxial layer, which can suppress the beta gain
37、 of parasiticBJT and therefore reduce the overall leakage current of diodestrings. However, epitaxy is a quite costly process step, so thatmost consumer IC products are not fabricated on epitaxial sub-strate if they have to compromise with their costs. Therefore,diode strings fabricated on a 0.35- m
38、 CMOS process withoutAuthorized licensed use limited to: Zhejiang University. Downloaded on December 9, 2008 at 10:17 from IEEE Xplore. Restrictions apply.et al.: DESIGN ON POWER-RAIL ESD CLAMP CIRCUIT FOR 3.3-V I/O INTERFACE2191Fig. 4. LeakagecurrentsofSTnMOSwithorwithoutthe ESDdetectioncircuitunde
39、r different temperatures.TABLE IILEAKAGECURRENT OFPRIORARTS AND THENEWPROPOSEDPOWER-RAILESD CLAMPCIRCUITepitaxial layer in 25 is compared with the proposed design ofthis work instead of diode strings in 22.B. Turn-On VerificationOne ofthemainbenefitsofthenewproposed power-railESDclamp circuit is to
40、enhance the turn-on speed of ESD clampdevice (STnMOS) during ESD stress conditions. The turn-onspeed of the STnMOS device with or without ESD detectioncircuit is measured in Fig. 5, where a voltage pulse with pulseheightof20Vandrisetimeof10nsisappliedtotheh.Thetimetoclampthe20-Vvoltagepulsetothehold
41、ingvoltagelevel(V)bythestand-aloneSTnMOSdeviceisaboutns,asshown in Fig. 5. Moreover, the overshooting peak voltage of thestand-alone STnMOS in Fig. 5 is aboutV, which could behigherthanthegate-oxidebreakdownvoltageofthelow-voltagedevicesintheinternalcircuits.Onthecontrary,the20-Vvoltagepulse can be
42、quickly clamped by the STnMOS with ESD detec-tion circuit to a low voltage level without overshooting. This re-sultverifiesthattheturn-onspeedoftheSTnMOScanbeindeedimproved by the proposed ESD detection circuit. The clampedvoltage level will be limited by the snapback holding voltage ofthe STnMOS de
43、vice, after the lateral n-p-n BJT in the STnMOSdevice is triggered on by the ESD detection circuit. From themeasured voltage waveforms in Fig. 5, the excellent turn-on ef-ficiency of the new proposed power-rail ESD clamp circuit hasbeen successfully verified. Therefore, the internal circuits canbe e
44、ffectively protected by the new proposed power-rail ESDclamp circuit in cooperation with the whole-chip ESD protec-tion schemes shown in Fig. 1.Fig. 5. The clamped voltage waveforms by STnMOS with or without the ESDdetection circuit under the voltage pulse stress with the pulse height of 20 V andthe
45、 rise time of 10 ns.Fig. 6. The measured substrate-triggered current generated by the ESD detec-tion circuit under 0-to-7 V voltage pulse with a rise time of 10 ns on theVhpin.To verify the effectiveness of the ESD detection circuit in theproposed power-rail ESD clamp circuit, a measurement setup is
46、shown in the inset of Fig. 6 to observe the substrate-triggeredcurrent. In the specially drawn testchip, the output node of astand-alone ESD detection circuit is also connected to anotherpad. The substrate trigger node of a stand-alone STnMOS isconnected to a pad. In the circuit board, the output no
47、de of astand-alone ESD detection circuit is connected to the substratetriggernodeofastand-aloneSTnMOSbyawiredline.Acurrentprobe is used to measure the transient current flowing throughthis wired line. With such measurement setup, the measuredsubstrate-triggered current generated by the ESD detection
48、 cir-cuit under 0-to-7 V voltage pulse with a rise time of 10 ns ontheh pin is shown in Fig. 6. The substrate-triggered cur-rent almost simultaneously appears with a peak current ofmA, when the 0-to-7 V voltage pulse is applied toh pin.So,theSTnMOSwithESDdetectioncircuitcanbequicklytrig-gered on to
49、clamp the overstress ESD voltage, as the clampedvoltage waveform shown in Fig. 5. After 800 ns, the voltage atthegateofthepMOSMp1followsupthegiven0-to-7VvoltageAuthorized licensed use limited to: Zhejiang University. Downloaded on December 9, 2008 at 10:17 from IEEE Xplore. Restrictions apply.I: REG
50、ULAR PAPERS, VOL. 53, NO. 10, OCTOBER 2006TABLE IIIESD ROBUSTNESS OFSTNMOS DEVICESWITH ORWITHOUT THENEWPROPOSEDESD DETECTIONCIRCUITtransient. Therefore, the ESD detection circuit is turned-off andthe measured trigger current drops to zero. The timing for thegate voltageof Mp1 to follow upthe transie
51、ntvoltageappliedtoh pin can be controlled by changing the R1 and C valuesand is designed to distinguish between the power-on transitionand the ESD transition.C. ESD RobustnessWith sufficient substrate-triggered current, the STnMOScan be directly triggered into its holding region without snap-back sw
52、itching. Therefore, the turn-on speed of the proposedpower-rail ESD clamp circuit can be significantly improved toeffectively protect the internal circuits with low-voltage devicesand thin gate oxide 28. Moreover, the substrate-triggered cur-rent can uniformly trigger on the STnMOS under ESD stress,
53、so that the STnMOS with a larger device dimension results in asmaller turn-on resistance in the pulsed IV response. To keepa lower overshooting voltage during ESD stress, the STnMOSwith large enough device dimension should be chosen whenthe internal circuits are implemented with the low-voltagedevic
54、es 28. Table III summarizes the human-body- model(HBM) 1 ESD robustness and the machine-model (MM) 2ESD robustness of the STnMOS devices with and without theESD detection circuit. Measurement results have shown greatimprovement on ESD robustness of the STnMOS with the ESDdetection circuit, as compar
55、ing with that of the stand-aloneSTnMOS devices. The HBM and MM ESD levels are measuredby KeyTek ZapMaster and the devices are judged ESD failureif their IV characteristic curves shift over 20% after threecontinuous ESD zaps at every ESD test level.D. SCR as ESD Clamp DeviceThe SCR device, which is c
56、omposed of cross-coupled n-p-nand p-n-p BJTs with regenerative feedback, has been foundto play an important role for ESD protection in very deepsub-micron CMOS technologies. However, main concerns ofthe SCRdevice as ESD clampdevice are the slow turn-onspeedand the higher switching voltage (). The su
57、bstrate-triggeredtechnique has been reported as an effective method to lowertheand to increase the turn-on speed of SCR devices29. Therefore, as another choice of high-voltage tolerantESD clamp device, the ESD detection circuit in this work wasapplied on triggering the substrate of SCR devices. The
58、SCRdevices, both stand-alone and substrate-triggered, are in serieswith three diodes to increase its overall holding voltage to3.8 V to avoid the latch-up issue 30 The TLP measured IVFig. 7. TLP-measured IV characteristics of both SCR with and without ESDdetection circuit.curves of SCR with or witho
59、ut the proposed ESD detectioncircuit are shown in Fig. 7. In Fig. 7, the stand-alone SCR hasaas high as 15.9 V, which is unqualified for protectinginternal circuits during ESD transition. With the proposed ESDdetection circuit, thecan be greatly lowered to 5.6 V. Whenthe substrate-triggered SCR is 3
60、0m in width, the measuredIt2 isA. It is increased to be greater than 6 A when thesubstrate-triggered SCR is 90m in width. As a result of theloweredand the increased turn-on speed, SCR device withthe proposed ESD detection circuit is also an useful power-railESD clamp circuit to the 3.3-V mixed-volta
61、ge I/O interfaces.V. CONCLUSIONAnewpower-railESDclampcircuitrealizedwithlow-voltage devices for 1-V/3.3-V mixed-voltage I/O in-terface has been successfully verified in a 130-nm 1-V/2.5-VCMOS process. As comparing to the stand-alone STnMOS,the turn-on speed of the STnMOS can be effectively improvedb
62、y the proposed ESD detection circuit. As well as, its HBM(MM) ESD level can be improved from 1 kV (150 V) to 3.75kV (250 V) for the STnMOS with a device dimension (W/L)ofmm. The ESD detection circuit has also shownsignificant help on lowering theof SCR devices. This newproposed power-rail ESD clamp
63、circuit with the advantagesof very low leakage current, fast turn-on speed, higher ESDrobustness, and no gate-oxide reliability issue is an excellentESD protection solution to the mixed-voltage I/O interface withhigh-voltage I/O signals.REFERENCES1 ESD Test Standard for Electrostatic Discharge Sensi
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81、ou Ker (S92M94SM97) received theB.S. degree in electronics engineering and the M.S.and Ph.D. degrees in electronics from the NationalChiao-Tung University, Hsinchu, Taiwan, R.O.C., in1986, 1988, and 1993, respectively.In 1994, he joined the Very Large Scale Inte-gration (VLSI) Design Department, Com
82、puter andCommunicationResearchLaboratories(CCL),Industrial Technology Research Institute (ITRI),Hsinchu, Taiwan, R.O.C., as a Circuit Design En-gineer. In 1998, he became a Department Managerwith the VLSI Design Division, CCL/ITRI. Currently he is a Full Professor inthe Department of Electronics Eng
83、ineering, National Chiao-Tung University.He has been invited to teach or help electrostatic discharge (ESD) protectiondesign and latchup prevention by hundreds of design houses and semiconductorcompanies in Taiwan, R.O.C.; Silicon Valley, San Jose, CA.; Singapore; andMainland China. His research int
84、erests include reliability and quality designfor nanoelectronics and gigascale systems, high-speed or mixed-voltage I/Ointerface circuits, special sensor circuits, and thin-film transistor (TFT) circuts.In the field of reliability and quality design for CMOS integrated circuits(ICs), he has authored
85、 or coauthored over 270 technical papers in internationaljournals and conferences. He has invented hundreds of patents on reliabilityand quality design for ICs, which have been granted with 112 U.S. patents and122 Taiwan patents. His inventions on ESD protection designs and latchupprevention methods
86、 have been widely used in modern IC products.Dr. Ker has serviced as member of the Technical Program Committee, Sub-Committee Chair, and Session Chair of numerous international conferences. Heis currently serving as Associate Editor for the IEEE TRANSACTIONS ONVERYLARGESCALEINTEGRATION(VLSI) SYSTEMS
87、. He was elected as the first Pres-ident of the Taiwan ESD Association in 2001. He has also been the recipientof numerous research awards presented by ITRI, the National Science Council,NationalChiao-TungUniversity,andtheDragon ThesisAwardpresentedbytheAcer Foundation. In2003, he wasselected as one
88、of the Ten OutstandingYoungPersons in Taiwan, R.O.C., by the Junior Chamber International (JCI). One ofhisinventionshasbeenawardedwithTaiwanNationalInventionAwardin2005.Wen-Yi Chen was born in Taiwan in 19 8 1. Hereceived the B .S. degree in electronics engineeringand the M.S. degree from the Instit
89、ute of Electronics,N ational Chiao-Tung U niversity, Hsinchu, Taiwan,R .O.C., in 2003 and 2005, respectively.He is currently with the Chinese army for militaryservice. His researches are related to on-chip ESDprotection design in CMOS integrated circuts,especially in the field of high-voltage tolera
90、ntapplications.Kuo-Chun Hsu (S01M03) received the B.S.degree in electronics engineering from NationalChung-Hsing University, Taichung, Taiwan, R.O.C.,in 1998 and the M.S. and Ph.D. degrees from theInstitute of Electronics, National Chiao-Tung Uni-versity, Hsinchu, Taiwan, R.O.C., in 2000 and 2003,re
91、spectively.In 2004, he joined the Mixed-Signal DesignDepartment, Global UniChip Corporation, Sci-ence-BasedIndustrialPark,Hsinchu,Taiwan,R.O.C., as a Principal Engineer. His main researchincludes mixed-signal circuit design and electrostatic discharge protectioncircuit design.Dr. Hsu was awarded with the Dragon Thesis Award by Acer Foundation,Taiwan, in 200 for his Ph.D. dissertation. He was elected an honorary memberof the Phi Tau Phi Society.Authorized licensed use limited to: Zhejiang University. Downloaded on December 9, 2008 at 10:17 from IEEE Xplore. Restrictions apply.
