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1、DDR3 /调试 Kade Huang2013.11;.DDR/DDR2/DDR3比较2DDR2/DDR3 比较之PIN脚DDR2 only contain Vref pin,DDR3 has Vrefca and Vrefdq which are used as command/address and data reference.DDR3 add a RESET# pin for asynchronous resetDDR3 add a ZQ PIN for internal ZQ calibration reference. ZQ Calibration command is used
2、to calibrate DRAM Ron & ODT values. For more detail, refer to Page 107 of DDR3 Standard(JESD79-3E).3DDR2/DDR3 比较之layout4DDR3 layout analyze5DDR3 之Write leveling6DDR3 之Write leveling 实现方式7DDR3 测试之读写分离DDR3写操作时，DQS write preamble 在一个clk周期内先高后低，如下图所示：8DDR3 测试之读写分离(续)DDR3读操作时，DQS read preamble为一个clk周期的低电
3、平，如下图所示：9DDR2/DDR3 比较之CWLCWL：CAS write latency, its only defined in DDR3. In DDR2, WL = RL-1.10DDR 参数之CLCL：CAS Latency 1. CAS latency is the delay, in clock cycles, between the internal Read command and availability of the first bit of output data. 2. programmable CAS Latency 5,6,7,8,9,10,11,12,13 3
4、. CL is only decided by DRAM . Ps, BL: Burst length11DDR 参数之tRCDtRCD: RAS to CAS delay time(activate to read/write interval of SDRAM.)tRCD is only decided by DRAM.12DDR 参数之tRPtRP: row precharge time 1.When need to read or write other row, the precharge command is used. tRP is the time that precharge
5、 to row. 2. tRP is only decided by DRAM.13DDR3 简单debug（以P2010为例）tDSS,tDQSS,tDSH 时序不满足时tDSS,tDQSS,tDSH定义如下：14tDSS,tDQSS,tDSH 时序不满足(续)下图为未使用WRLVL_EN功能波形，tDSS不满足要求15tDSS,tDQSS,tDSH 时序不满足(续)使用DDR3 WRLVL_EN后tDSS满足要求，波形如下：16DQ读写波形有较大overshoot如下图，当写时DQS，DQ上存在较大的振铃。此时DRAM端ODT设置为120ohm.17DQ写波形有较大overshoot(续)将DRAM测ODT修改为60ohm后测试波形如下:18DQS读信号回沟位置调整当测试读信号时，DQS上升沿会存在回沟，如下图所示，此回沟可导致DQS误触发可使用调整CPU内部ODT的方式进行调整。19
