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1、版图绘制版图绘制及及Virtuoso的使用的使用1.典型深亚微米工艺流程2.Design Rule的简介3.Virtuoso软件的简介及使用4.版图设计中的相关主题7/30/20242共85页1 典型深亚微米工艺流程这里介绍目前比较普通的N阱CMOS工艺流程，用到的wafer是p型衬底，所以需要用nWELL来构建p沟器件，而n型MOS管就构建在p衬底上，而对于SMIC工艺来讲，NMOS构建在nWELL的反版也就是pWELL中。7/30/20243共85页第一张mask定义为n-well(or n-tub)maska)离子注入：制造nwell。b)扩散：在所有方向上扩散，扩散越深，横向也延伸越多
2、。7/30/20244共85页第二张mask定义为active mask。 有源区用来定义管子的栅以及允许注入的p型或者n型扩散的管子的源漏区。7/30/20245共85页忽略版图中无法体现的一些mask：诸如channel stop、阈值电压调整等要介绍的第三张mask为poly mask：它包含了多晶硅栅以及需要腐蚀成的形状。这还用来定义源漏的自对准。7/30/20246共85页第四张mask定义为nmask，用来定义需要注入n的区域。可以看到多晶硅栅用来作为源漏的自对准层。这里的注入为两次注入，首先轻掺杂注入，在栅上生成一层氧化层后再重掺杂注入，形成LDD结构。7/30/20247共85
3、页第五张mask是pmask。p在Nwell中用来定义PMOS管或者走线；p在Pwell中用来作为欧姆接触。LDD不必用来形成PMOS，这是因为热载流子在PMOS中受影响小。7/30/20248共85页第六张mask就是定义接触孔了。首先腐蚀SiO2到需要接触的层的表面。其次要能够使金属接触到扩散区或者多晶硅区。7/30/20249共85页第七张mask就是金属1（metal1）了。需要选择性刻蚀出电路所需要的连接关系。至此，一个反相器的完整版图就完成了。7/30/202410共85页2 Design Rule的简介图解术语7/30/202411共85页7/30/202412共85页7/30/
4、202413共85页一个简单的例子7/30/202414共85页3 Virtuoso软件的简介及使用You use the Virtuoso layout tools to prepare custom integrated circuit designs. Create and edit polygons, paths, rectangles, circles, ellipses, donuts, pins, and contacts in layout cellviewsPlace cells into other cells to create hierarchical designsC
5、onnect a pin or group of pins in a net internally or externallyCreate special pcells or use SKILL language commands7/30/202415共85页Starting the Layout EditorTo start the Virtuoso layout editor software, you must type the name of an executable in an xterm window.nlayout includes the layout editor, Ass
6、ura internactive verification products, plotting, and physical translatorsnlayoutPlus includes all of the above, plus the Virtuoso compactor and Virtuoso XLnicfb includes all cadence custom IC design tools, front to back design environment7/30/202416共85页Create Layout CellviewFile-New-Cellview7/30/20
7、2417共85页Virtuoso Layout Editor Design Window7/30/202418共85页Using the Icon Menu7/30/202419共85页Controlling the Icon MenuYou can control CIW-Option-UserWhere the icon menu appearsWhether the menu appears at allWhether icon names appear7/30/202420共85页Layout Editor 菜单（1）Abstract用于版图抽取，Dracula Interactive
8、用于Dracula工具进行DRC等Verify菜单下的DRC等是用于Diva工具的。7/30/202421共85页Layout Editor 菜单（2）7/30/202422共85页Setting Up Your EnvironmentSetting Layout Editor Defaults:Before you can start working in the Virtuoso layout editor, several startup files must be initiated. Some of the things these files do include setting
9、up your environment, pointing to libraries, and defining your plotters.7/30/202423共85页Startup FilesFile.cdsenvPurposeHolds application defaults for environment variables.User location/.cdsenvSample locationyour_install_dir/tools/dfII/samples/.cdsenvSystem default location./.cdsenv7/30/202424共85页File
10、.cdsinitPurposeA Cadence SKILL language file executed when the Cadence design framework II (DFII) product starts.User location/.cdsinitSample locationyour_install_dir/tools/dfII/samples/local/cdsinitSystem default location ./.cdsinitFilecds.libPurposeSets the paths to libraries and other cds.lib fil
11、es. INCLUDE your_install_dir/share/cdssetup/cds.lib7/30/202425共85页File.cdsplotinitPurposeInitialization script for plot operations.User location /.cdsplotinitSample locationyour_install_dir/tools/plot/samples/cdsplotinit.sampleSystem default location./.cdsplotinit7/30/202426共85页Filedisplay.drfPurpos
12、eSpecifies how you want your layers to appear on your monitor and in your plots.User location /display.drfSample locationyour_install_dir/share/cdssetup/dfII/default.drfSystem default location./display.drf7/30/202427共85页Using the Display Options Form7/30/202428共85页Using the Layout Editor Options For
13、m7/30/202429共85页Layer Selection Window(LSW)The LSW lets you choose the design layer for each shape you create, make design layers visible or invisible, or make instances and pins selectable or unelectable.7/30/202430共85页Setting Valid LayersChoose Edit Set Valid Layers in the LSW7/30/202431共85页Making
14、 One Layer Selectable or UnselectableIn the LSW, click middle on the layer.The layer color disappears. The layer name is shaded, to show that the layer is also unselectable.7/30/202432共85页Making All but One Layer UnselectableIn the LSW, press Shift and click middle on the layer you want to be the on
15、ly selectable layer.7/30/202433共85页Using SearchThe Search command lets you search for objects with specific attributes or property values.7/30/202434共85页Virtuoso下的快捷键的使用（1）CtrlA 全选ShiftB Return，升到上一级视图CtrlC 中断某个命令，一般用ESC代替。ShiftC 裁切（chop）。C 复制。复制某个图形CtrlD 取消选择。亦可点击空白处实现。CtrlF显示上层等级ShiftF显示所有等级F fit，
16、显示你画的所有图形K 标尺工具ShiftK清除所有标尺。L 标签工具M 移动工具ShiftM 合并工具，MergeN 斜45对角正交。ShiftO 旋转工具。RotateO 插入接触孔。CtrlP 插入引脚。 PinShiftP 多边形工具。PolygonP 插入Path。路径。Q 图形对象属性。选中一个图形先R 矩形工具。绘制矩形图形。S 拉伸工具。可以拉伸一个边。也可以选择要拉伸的组一起拉伸。U 撤销。 Undo。ShiftU重复。Redo。撤销后反悔7/30/202435共85页Virtuoso下的快捷键的使用（2）V 关联attach。将一个子图形（child）关联到一个父图形（par
17、ent）后，若移动parent，child也跟着移动；移动child，parent不会移动。CtrlW 关闭窗口。ShiftW下一个视图。W 前一个视图。Y 区域复制Yank。和copy有区别，copy只能复制完整图形对象。ShiftY 黏贴Paste。配合Yank使用。CtrlZ 视图放大两倍。ShiftZ 视图缩小两倍。Z 视图放大。ESC键 撤销功能。Tab键 平移视图Pan。按Tab，用鼠标点击视图区中某点，视图就会移至以该点为中心。Delete键键 删除。BackSpace键键 撤销上一点。这就不用因为Path一点画错而删除重画。可以撤销上一点。Enter键 确定一个图形最后一点。也
18、可以双击鼠标左键。Ctrl方向键 移动Cell。Shift方向键 移动鼠标。方向键方向键 移动视图。7/30/202436共85页Design Access ProblemsI Cant Find a LibrarynThe library path in the cds.lib file is incorrectnThe library is not in the cds.lib fileTo fix either of these problems, - Edit your cds.lib file.7/30/202437共85页I Cant Open a CellviewIf you c
19、annot open a cellview in a library, you might not have read access to the cellview files.To gain read access to the cellviews in a library, - Do one of the following:pChange the access permissions using the Library Manager Edit Access Permissions form.pUse the UNIX command chmod to change the access
20、 permissions in the UNIX directory containing the library.7/30/202438共85页I Cant Write to a CellviewIf you have write access to a library but cannot open a cellview to edit.nYou do not have write access for the cellview filenAnother user is editing the cellview and locked it-Do one of the following:p
21、Change the access permissions using the Library Manager Edit Access Permissions form.pUse the UNIX command chmod to change the access permissions in the UNIX directory containing the library.7/30/202439共85页Cell Instances Are MissingA cellview often contains instances of cells from other design libra
22、ries. If you open a cellview that contains instances of cells from a library that the layout editor cannot find, the following happens:nWhen you try to open the cellview, you see a warning dialog box listing cells that the layout editor cannot findnWhen you close the dialog box, the cellview opens,
23、but each area containing a missing cell displays a flashing box with an X7/30/202440共85页These ares contain cell instances from a library that the layout editor cannot find.To include the missing cells,- Add the path to the library containing the cell masters to the cds.lib file.7/30/202441共85页Right
24、Mouse Button Doesnt WorkBy default, the right mouse button works as follow:nTo repeat the last command, click right oncenTo zoom in, press and hold right and create a boxnTo zoom out, press the Shift key and hold right and create a boxnTo change options while using some editing commands, press and h
25、old right7/30/202442共85页If the right mouse button will not do any of these tasks, it is probably set to create strokes.nTo cancel the stroke-creation capability, you must exit and restart the Cadence software.nTo remove the stroke commands from your .cdsinit file. Type a semicolon (;) in front of st
26、roke.il, defstrokes.il, def.strokes.7/30/202443共85页How to Select Objects in a Dense DesignIf you click on objects in a dense design and the layout editor does not select the object you want, try any of the following:nIf objects share the edge you chose, click again in the same place.nIf possible, mo
27、ve the cursor closer to another edge of the object and click.nIf possible, zoom in on the edge you want to select.nUse the LSW7/30/202444共85页About MessagesThere are four types of messages:7/30/202445共85页Working With MarkersTo get information about a marker, use these commands:nVerify - Markers - Exp
28、lain displays the reason for the error or warning marker in a text windownVerify - Markers - Find searches for and highlights each error or warning markerAfter you get the information you need, you can delete the marker using these commandsnVerify - Markers - Delete removes a specific markernVerify
29、- Markers - Delete All removes all markers 7/30/202446共85页4 版图设计中的相关主题1.Antenna Effect2.Dummy 的设计3.Guard Ring 保护环的设计4.Match的设计7/30/202447共85页4.1 Antenna Effect原因：大片面积的同层金属。导致：收集离子，提高电势。结果：使氧化层击穿。解决如下：7/30/202448共85页0.13um CMOS工艺中的天线规则CT与有源区栅面积VIA与有源区栅面积累积Metal与有源区栅面积有二极管保护的累积Metal与有源区栅面积保护管面积大小对天线效应
30、的影响7/30/202449共85页4.2 Dummy 的设计IC版图除了要体现电路的逻辑或功能确保LVS验证正确外，还要增加一些与LVS（电路匹配）无关的图形，以减小中间过程中的偏差，我们通常称这些图形为dummy layer。有些dummy layer是为了防止刻蚀时出现刻蚀不足或刻蚀过度而增加的，比如metal density不足就需要增加一些metal dummy layer以增加metal密度。另外一些则是考虑到光的反射与衍射，关键图形四周情况大致相当，避免因曝光而影响到关键图形的尺寸。 7/30/202450共85页a、MOS dummy在MOS两侧增加dummy poly，避免L
31、ength受到影响。添加dummy管，可以提供更好的环境一致性7/30/202451共85页b、RES dummy类似于MOS dummy方法增加dummy，有时会在四周都加上。7/30/202452共85页c、CAP dummy7/30/202453共85页d、Interconnect关键走线与左右或上下走线的屏蔽采用相同层或中间层连接VSS来处理。也可增大两者间的间距来减少耦合。7/30/202454共85页4.3 Guard Ring的设计7/30/202455共85页保护环分两种：多数载流子保护环 、少数载流子保护环 。少数载流子保护环是掺杂不同类型杂质，形成反偏结提前收集引起闩锁的注
32、入少数载流子。多数载流子保护环是掺杂相同类型杂质，减小多数载流子电流产生的降压。 7/30/202456共85页深阱guard ring的应用SMIC提供深阱工艺（DNW），可以用来有效隔离不同模块间的噪声。这种隔离保护技术只应用在1.8V情况下。且只对NMOS管进行保护。7/30/202457共85页4.4、Match的设计a、MOS的match对于大的宽长比的MOS管，常采用多指结构，降低栅电阻，减少噪声，提高工作的频率。但是过多的fingers则是不利的。7/30/202459共85页MOS管的对称性差分对管：7/30/202460共85页工艺梯度的影响采用中心对称结构能够解决工艺梯度对
33、电路性能的影响。缺点是走线的复杂性增加，可能带来其他不利的寄生效应的影响。7/30/202461共85页一维中心对称的MOS管layout7/30/202462共85页其它一些MOS匹配的例子：7/30/202463共85页交叉对称（1）7/30/202464共85页交叉对称（2）7/30/202465共85页b、RES 的匹配一维对称结构：7/30/202466共85页交叉对称7/30/202467共85页c、PNP管对称：7/30/202468共85页Modeling RF IC Packages n在PCS及无线通信中工作在射频段的器件日益增长，射频IC封装的寄生效应越发显得重要，诸如：
34、阻抗失配、高频谐振以及pins和键合线之间的串扰等问题。这样有必要对系统进行精确的仿真，而精确的仿真需要这些寄生效应的精确模型。n对于IC封装有很多种类型，95的IC封装采用SOIC（small outline IC）、QFP（quad flat pack）以及DIP（dual inline package）。基于这样的资讯，一款RF IC封装的建模工具被开发出来了。7/30/202470共85页厂商提供的封装示意图7/30/202471共85页启动ZUEDA3% pkg &ZUEDA3% sourcing /opt/ic5033/tools/dfII/etc/pkg/init.coeffge
35、nsourcing /opt/ic5033/tools/dfII/etc/pkg/init.pkgdone.PKG的核心n物理几何尺寸建模模块n网状EM解决器n用来计算电容电感的3D EM解决器n后处理模块 7/30/202472共85页PKG支持的封装类型 nSOIC 包括SSOP、TSSOP、VSOnQFP 包括TQFP、LQFPnDIP7/30/202473共85页Package Physical Geometry Moedlingn封装的体，一般是塑料或者陶瓷nlead frame，包括了pins和die的连接n键合线ndie 7/30/202474共85页The PKG RF IC
36、Package Modeler Form7/30/202475共85页Option7/30/202476共85页Package Dimension Setup 7/30/202477共85页Die Attach Setup7/30/202478共85页Internal Lead Frame Setup 7/30/202479共85页Bond Wire Setup 7/30/202480共85页Parameter Extraction 7/30/202481共85页Macromodel Generation 最终在运行的目录下生成一个pkg.proj文件夹，cd进去后可以找到我们需要的rfpkg
37、.scs文件，或者上图所填Macromodel Name.scs。这里建议填入rfpkg。避免后面仿真时symbol与subckt名称不匹配。7/30/202482共85页Simulation of Package Models in the Analog Circuit Design Environment 从rfExamples库中调用rfpkg的symbol。左边代表了封装外部的pins。右边的端口代表了die上的键合线的压焊块。 7/30/202483共85页修改库文件进行仿真n打开pkg生成的*.scs文件，在文件头尾分别添加如下语句：library any_namesection ttendsection ttendlibrary any_namen仿真时在添加仿真库文件时添加该*.scs文件即可。7/30/202484共85页谢谢！
