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1、第四章基本数字逻辑单元的设计基本数字逻辑单元的设计Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.4.1 组合逻辑设计组合逻辑设计4.1.2 三态缓冲器和总线缓冲器三态缓冲器和总线缓冲器 8b
2、it单向总线缓冲器单向总线缓冲器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tri_buf8 IS PORT (din：IN STD_LOGIC_VECTOR (7 DOWN TO 0); dout：OUT STD_LOGIC_VECTOR (7 DOWN TO 0); en：IN STD_LOGIC); END tri_buf8; Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspo
3、se Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.ARCHITECTURE data_flow OF tri_buf8 IS PROCESS (en, din) BEGIN IF (en=1) THEN dout = din; ELSE dout = ZZZZZZZZ; END IF; END PROCESS; END data_flow ;Endin(0)din(1)din(2)din(3)di
4、n(4)din(5)din(6)din(7)dout(0)dout(1)dout(2)dout(3)dout(4)dout(5)dout(6)dout(7)Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pt
5、y Ltd. 双向总线缓冲器双向总线缓冲器 用用VHDL语言描述的双向总线缓冲器。语言描述的双向总线缓冲器。 en dir 功能功能 1 X 高阻态高阻态 0 0 a=b 0 1 b=aadirenb LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dobl_tri_buf8 IS PORT (a, b：INOUT STD_LOGIC_VECTOR (7 DOWN TO 0); dir, en：IN STD_LOGIC); END dobl_tri_buf8； Evaluation only.Created with Aspose.Slide
6、s for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. ARCHITECTURE rtl OF dobl_ tri_buf8 IS SIGNAL aout, bout：STD_LOGIC_VECTOR (7 DOWN TO 0 ); BEGIN P1: PROCESS (a, d
7、ir, en) BEGIN IF (en=0) AND (dir=1) THEN bout = a; ELSE bout =ZZZZZZZZ; END IF; b = bout; END PROCESS P1; Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.C
8、opyright 2004-2011 Aspose Pty Ltd. P2: PROCESS (b, dir, en) BEGIN IF (en=0) AND (dir=0) THEN aout = b; ELSE aout = ZZZZZZZZ; END IF a q q q q q q q q q q q =11111111; END CASE;END seg_rtl;Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Lt
9、d.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. 4.1.4 运算器的设计运算器的设计 一位全加器的设计一位全加器的设计. LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL；ENTITY full_adder ISPORT (a, b, ci： IN STD_LOGIC; sum, cout： OUT STD_LOGIC);END full_adder; ARCHITECTURE
10、rtl OF full_adder IS BEGIN sum = a XOR b XOR ci； cout = (a AND b) OR (a AND ci ) OR ( b AND ci)； END rtl;a sumb ci cout Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Pro
11、file 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.4 4位串行进位加法器位串行进位加法器 ci a bsum coci a bsum coci a bsum coci a bsum co S0 S1 S2 S3 CO CI A0 B0 A1 B1 A2 B2 A3 B3 SUM CI A BSUM CI A BSUM CI A BSUM CI A B CI0 A0 B0 CI1 A1 B1 CI2 A2 B2 CIn-1 An-1 Bn-1 进位产生逻辑进位产生逻辑S0S1S3Sn-1coutCI A0: n-1 B0: n-1N位超位超前进位前进
12、位加法器加法器Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.超前进位加法器超前进位加法器 各位加法器产生进位的逻辑表达式为：各位加法器产生进位的逻辑表达式为：定义定义 为进位生成函数为进位生
13、成函数,定义定义 为进位传递函数为进位传递函数, 则则全加器的各位和为：全加器的各位和为：Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.4位超前进位加法器位超前进位加法器LIBRARY IE
14、EE;USE IEEE STD_LOGIC_1164.ALL;ENTITY adder4 IS PORT (a, b：IN STD_LOGIC_VECTOR (3DOWN TO 0 ) ci：IN STD_LOGIC; sum：OUT STD_LOGIC_VECTOR (3 DOWN TO 0 ); cout：OUT STD_LOGIC);END adde4r；ARCHITECTURE rtl_adder4 OF adder4 IS SIGNAL g, p, c：STD_LOGIC_VECTOR (3 DOWN TO 0 )； BEGIN p(0) = a(0) OR b(0); p(1) =
15、 a(1) OR b(1); p(2) = a(2) OR b(2); g(0) = a(0) AND b(0);a3:0b3:0ciSum3:0coutEvaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty
16、 Ltd. g(1) = a(1) AND b(1); g(2) = a(2) AND b(2); g(3) = a(3) AND b(3); c(0) = g(0) OR (p(0) AND ci ); c(1) = g(1) OR (p(1) AND g(0) OR (p(1) AND p(0) AND ci); c(2) = g(2) OR (p(2) AND g(1) OR (p(2) AND p(1) AND g(0) OR (p(2) AND p(1) AND p(0) AND ci); c(3) = g(3) OR (p(3) AND g(2) OR (p(3) AND p(2)
17、 AND g(1) OR (p(3) AND p(2) AND p(1) AND g(0) OR (p(3) AND p(2) AND p(1) AND p(0) AND ci); cout = c(3); sum(0) = a(0) XOR b(0) XOR ci; sum(1) = a(1) XOR b(1) XOR c(0); sum(2) = a(2) XOR b(2) XOR c(1); sum(3) data_out data_out data_out data_out = data_in; END CASE; END PROCESS; END Alg; Evaluation on
18、ly.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.3. 求补器求补器 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL；USE IEEE.STD_LOGIC_ARITH.ALL;USE I
19、EEE.STD_LOGIC_UNSIGNED.ALL;ENTITY complement IS PORT (a：IN STD_LOGIC_VECTOR (7 DOWN TO 0); b：UT STD_LOGIC_VECTOR (7 DOWN TO 0); END complement; ARCHITECTURE rtl OF complement IS BEGIN b = NOT a +”00000001”； END rtl;Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyri
20、ght 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. 4. 乘法器。乘法器。 部分积右移部分积右移8bit乘法器的设计。乘法器的设计。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY mult IS
21、 PORT (ai, bi：IN STD_LOGIC_VECTOR (7 DOWN TO 0); Product：OUT STD_LOGIC_VECTOR (15 DOWN TO 0); done：OUT STD_LOGIC); END mult; Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Clien
22、t Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.ARCHITECTURE shift_mult OF mult ISBEGIN PROCESS (ai, bi) VARIABLE a, b, m：STD_LOGIC_VECTOR (8 DOWN TO 0); VARIABLE count：INTEGER; BEGIN a: = 0 & ai; b: =0 & bi; count: = 0; m: = 00000000; done = 0; Evaluation only.Created with Aspose.Slides for .N
23、ET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.WHILE count 8 LOOP IF a(0) = 1 THEN m: = m+bi; END IF; a: = m(0) & a(7 DOWN TO 1); m: = 0 & m(7 DOWN TO 1); count: = coun
24、t+1; END LOOP; product = m(7 DOWN TO 0) & a(8 DOWN TO 1); done = 1; END PROCESS; END shift_mult;Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2
25、004-2011 Aspose Pty Ltd. 4.1.5 算术逻辑运算单元算术逻辑运算单元 本例是一个本例是一个8bit的的ALU，能够完成，能够完成8种运算，即加种运算，即加(add)，带进位加，带进位加(addc)，减，减sub，带借位减法，带借位减法(subc)，逻辑，逻辑非、与、或和逻辑异或。非、与、或和逻辑异或。alucoder程序包定义指令码。程序包定义指令码。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE alucoder ISCONSTANT add：STD_LOGIC_VECTOR (2 DOWNTO 0): = 000;
26、CONSTANT addc：STD_LOGIC_VECTOR (2 DOWN TO 0): = 001;CONSTANT sub：STD_LOGIC_VECTOR (2 DOWN TO 0): = 010;Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copy
27、right 2004-2011 Aspose Pty Ltd.CONSTANT subc：STD_LOGIC_VECTOR (2 DOWN TO 0): = 011;CONSTANT not：STD_LOGIC_VECTOR (2 DOWN TO 0): = 100;CONSTANT and：STD_LOGIC_ VECTOR (2 DOWNTO 0): = 101; CONSTANT or：STD_ LOGIC_VECTOR (2 DOWN TO 0): = 110; CONSTANT xor：STD_LOGIC_VECTOR (2 DOWN TO 0): = 111 END alucode
28、r;Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.ALU运算模块设计。运算模块设计。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL； USE IEEE_
29、NUMERIC_STD.ALL； USE IEEE.STD_LOGIC_ARITH.ALL； USE IEEE.STD_LOGIC_UNSICNED.ALL； USE WORK.alucoder.ALL；ALU salu_comand cyAcc cout over Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET
30、3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. ENTITY alu IS PORT (s：IN STD_LOGIC_VECTOR (7 DOWN TO 0); cy：IN STD_ LOGIC; alu_comand：IN STD_LOGIC_VECTOR (2 DOWN TO 0); Acc： INOUT STD_LOGIC_VECTOR (7 DOWN TO 0); cout, over：BUFFER STD_LOGIC); END alu； ARCHITECTURE alg OF alu IS SIGNAL
31、r1, s1, f1：STD_LOGIC_VECTOR (8 DOWN TO 0); BEGIN r1 = 0 & Acc; s1 f1 IF cy = 0 THEN f1 = r1+s1； ELSE f1 f1 IF cy = 0 THEN f1 = r1+NOT (s1)+1； ELSE f1 f1 f1 f1 f1 f1 = -； Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.
32、Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. END CASE； END PROCESS； Acc = f1 (7 DOWN TO 0 )； cout = f1 (8 )； over = f1(8) XOR f1(7); END alu;Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose
33、 Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. 4.2时序逻辑电路设计时序逻辑电路设计 4.2.1 触发器触发器 1. D触发器触发器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL； ENTITY dff IS PORT (d, clk：IN STD_LOGIC； q：OUT STD_LOGIC )； END dff； ARCHITECTURE rtl_if
34、OF dff IS BEGIN PROCESS (clk) BEGIN Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. IF (clk EVENT AND clk = 1) THEN q =
35、 d； END IF； END PROCESS； END rtl_if； 结构体的另一种描述如下：结构体的另一种描述如下： ARCHITECTURE rtl_wait OF dff IS BEGIN PROCESS BEGIN WAIT UNTIL clk EVENT AND clk = 1； q = d； END PROCESS; END rtl_wait； Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Eval
36、uation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.4.2.3 寄存器寄存器 D0D7: 8位并行数据输入端。位并行数据输入端。SI: 串行数据输入端。串行数据输入端。Q7: 串行数据输出端。串行数据输出端。Q0Q6: 内部寄存器数据输出端。内部寄存器数据输出端。clk: 时钟。时钟。 ckin: 时钟信号禁止，只有当其时钟信号禁止，只有当其无效时，移位寄存器才在时钟的无效时，移位寄存器才在时钟的触发下进行移位操作。触发下进行移
37、位操作。 S/L: 移位（移位（shift）/装入（装入（load）。）。当此端为高电平时，可执行移位当此端为高电平时，可执行移位操作，当此端为低电平时，读入操作，当此端为低电平时，读入D0D7端的并行数据。端的并行数据。 CLR: 异步清零。异步清零。 D7:0 SI S/L Q7clk ckin clr Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with As
38、pose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. 串串/并入、串出移位寄存器并入、串出移位寄存器 LIBRARY IEEE； USE IEEE.STD_LOGIC_1164.ALL；ENTITY shifter IS PORT (clr, si, ckin, clk：IN STD_LOGIC； d：IN STD_LOGIC_VECTOR (7 DOWN TO 0 )； q：OUT STD_LOGIC )； sl：IN BIT )；END shifter；ATCHITECTURE
39、 rtl_shifter OF shifter IS SIGNAL temp8：STD_LOGIC_VECTOR (7 DOWN TO 0 )； BEGIN Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose P
40、ty Ltd. PROCESS (clr, sl, ckin, clk) IF (clr = 0 ) THEN temp8 = 00000000； q = temp8 (7)； ELSIF (clk EVENT ) AND (clk = 1 ) AND (ckin = 0 ) THEN IF (sl = 0) THEN temp8 = d； -装入数据装入数据 q = d (7)； ELSE q = temp8 (7)； temp8(7) = temp8(6)； temp8(6) = temp8(5)；Evaluation only.Created with Aspose.Slides for
41、 .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. temp8(5) = temp8(4)； temp8(4) = temp8(3)； temp8(3) = temp8(2)； temp8(2) = temp8(1)； temp8(1) = temp8(0)； temp8(0) = s
42、i； ENDIF； ENDIF； END PROCESS； END rtl_shifter； Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.4.2.4 计数器计数器 8位异步计数器的设计位异
43、步计数器的设计 Q /QD clkQ /QD clkQ /QD clkQ /QD clk d clkclrcount_in(0)count_in(1)count_in(8)Q0Q1Q2Q7Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 200
44、4-2011 Aspose Pty Ltd.计数器的顶层设计计数器的顶层设计LIBRARY IEEE；USE IEEE.STD_LOGIC_1164.ALL；ENTITY riplecount IS PORT (clk, clr：IN STD_LOGIC； count：OUT STD_LOGIC_VECTOR (7 DOWN TO 0)； END riplecount； ARCHITECTURE rtl_riplecount OF riplecount IS SIGNAL count_in：STD_LOGIC_VECTOR (8 DOWN TO 0)；Evaluation only.Creat
45、ed with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. COMPONENT dfft PORT (clk, clr, d：IN STD_LOGIC； Q：OUT STD_LOGIC; Qn：BUFFER STD_LOGIC)； END CO
46、MPONENT; -调用当前库中的同名实体作为元件调用当前库中的同名实体作为元件 BEGIN count_in (0) count_in(i)，clr = clr； d= count_in(i+1),，Q = count(i)； Qn = count_in(i+1)； END GENERATE； END rt_riplecountl；Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Cr
47、eated with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. -单个触发器性能描述单个触发器性能描述 LIBRARY IEEE； USE IEEE.STD_LOGIC_1164.ALL； ENTITY dfft IS PORT (clk, clr, d：IN STD_LOGIC； Q：OUT STD_LOGIC； Qn：BUFFER STD_LOGIC)； END dfft； ARCHITECTURE rtld OF dfft IS BEGINEvaluation
48、 only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. PROCESS (clk, clr) BEGIN IF (clr = 0) THEN Q = 0； Qn = 1； ELSIF (clk EVENT AND cl
49、k = 1) THEN Q = d； Qn = NOT d； END IF； END PROCESS； END rtld；Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.4.3 存储器存储器4
50、.3.1 概述概述 存储器单元实际上是时序逻辑电路的一种。按存储器存储器单元实际上是时序逻辑电路的一种。按存储器的使用类型可分为只读存储器的使用类型可分为只读存储器(ROM)和随机存取存储器和随机存取存储器(RAM)，两者的功能有较大的区别，因此在描述上也有，两者的功能有较大的区别，因此在描述上也有所不同。所不同。存储器是许多存储单元的集合，按单元号顺序排列。存储器是许多存储单元的集合，按单元号顺序排列。每个单元由若干二进制位构成，以表示存储单元中存每个单元由若干二进制位构成，以表示存储单元中存放的数值。这种结构和数组的结构非常相似，故在放的数值。这种结构和数组的结构非常相似，故在VHDL语言
51、中，通常由数组描述存储器。语言中，通常由数组描述存储器。 Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.TYPE memory IS ARRAY (INTEGER RANGE ) OF IN
52、TEGER； TYPE word IS STD_LOGIC_VECTOR (k-1 DOWN TO 0); TYPE memory IS ARRAY (0 TO w-1) OF word ;Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 20
53、04-2011 Aspose Pty Ltd.4.3.3 随机存储器随机存储器RAM LIBRARY IEEE； USE IEEE.STD_LOGIC_1164. ALL；USE IEEE.STD_LOGIC_ARITH.ALL； ENTITY ram4k IS GENERIC (k：INTEGER: = 8; w：INTEGER: = 12; rd_del, wr_del：TIME )； PORT (WR, RD, CS：IN STD_LOGIC； Adr：IN STD_LOGIC_VECTOR (w-1 DOWNTO 0)； D：INOUT STD_LOGIC_VECTOR (k-1 DO
54、WNTO 0)； END ram4k；WRRDCSAdr11:0Dout7:0Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.ARCHITECTURE behavram4k OF ram4k
55、ISTYPE memory IS ARRAY (0 TO 2*w-1) OF STD_LOGIC_VECTOR (k-1 DOWNTO 0)； SIGNAL sram：memory； SIGNAL Adr_in：INTEGER； BEGIN Adr_in = CONV_INEGER (Adr); -位矢量转换成整数位矢量转换成整数 PROCESS (WR, RD, CS) BEGINEvaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose P
56、ty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. IF CS = 0 THEN IF RD = 0 THEN D = sram (Adr_in) AFTER rd_del； ELSIF WR = 0 THEN sram (Adr_in) = D AFTER wr_del； ENDIF； ELSE D = (OTHERSZ) AFTER rd_del； END IF； END PROCESS； END b
57、ehav； Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.4.3.2 只读存储器只读存储器ROM 在用在用VHDL语言描述语言描述ROM时，时，ROM的内容应在仿真时的内容应在仿真时先读到先
58、读到ROM中，这就是中，这就是ROM的初始化。存储器的初始化的初始化。存储器的初始化要依赖于外部文件的读取，即由要依赖于外部文件的读取，即由TEXTIO对对ROM进行初进行初始化。下面是对始化。下面是对ROM进行初始化的实例。进行初始化的实例。 VARIABLE startup：BOOLEAN: = TRUE；VARIABLE l：LINE； - LINE是在是在TEXTIO程序包定义的存程序包定义的存取类型取类型VARIABLE j：INTEGER；VARIABLE rom：memory；FILE romin：TEXT IS IN rom2k.in; -TEXT 是在是在TEXTIO程序程序
59、包定义的文件类型包定义的文件类型Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.初始化程序：初始化程序： IF startup THEN FOR j IN rom RANGE LOOP -利用
60、数据区间属性函数获得利用数据区间属性函数获得 数组的上下限数组的上下限 READLINE (romin, l )； -从文件从文件romin中读入一行放入中读入一行放入l 中。中。 READ (l, rom(j)； -从从l中读入一个数据放入中读入一个数据放入rom中中 END LOOP； END IF； G1 G2Adr11;0Dout7:0Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation on
61、ly.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.只读存储器只读存储器ROM的的VHDL程序。程序。 LIBRARY IEEE；USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE STD.TEXTIO.ALL；ENTITY rom4k IS PORT (G1, G2：IN STD_LOGIC； Adr：IN STD_LOGIC_VECTOR (11DOWN TO 0)； do
62、ut: OUT STD_LOGIC_VECTOR (7 DOEN TO 0)； END rom4k; Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.ARCHITECTURE behav_ro
63、m4k OF rom4k IS TYPE word IS STD_LOGIC_VECTOR (7 DOWN TO 0)； TYPE memory IS ARRAY (0 TO 4095) OF word； SIGNAL adr_in：INTEGER RANGE 0 TO 4095； VARIBLE rom：memory； VARIBLE startup：BOOLEAN: = TURE； VARIBLE l：LINE； VARIBLE j：INTEGER； FILE romin：TEXT IS IN “rom2k.in”; -文件类说文件类说明明. BEGIN PROCESS (G1, G2)
64、BEGINEvaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. IF startup THEN FOR j IN rom RANGE LOOP READLINE (romin, l )； READ
65、 (l, rom(j)； END LOOP； startup: = FALSE； END IF； adr_in = CONV_INTEGER (Adr); -将位矢量转换成整数将位矢量转换成整数. IF (G1 = 1 AND G2 = 1) THEN dout = rom (adr_in)； ELSE dout = ZZZZZZZZ”; ENDIF; END PROCESS; END behav_rom2k； Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 200
66、4-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.4.3.4先进后出堆栈先进后出堆栈 先进后出堆栈是处理程序中断先进后出堆栈是处理程序中断的常用数据结构的常用数据结构,其数据存放结其数据存放结构和构和RAM是一致的，但存储方是一致的，但存储方式有所不同。式有所不同。 先进后出堆栈由先进后出堆栈由2个功能块组个功能块组成，即存储器体和堆栈指针成，即存储器体和堆栈指针SP，进堆时
67、进堆时SP+1SP指向下一个存指向下一个存储单元；出堆时储单元；出堆时SP-1 SP，并，并把把SP所指示的存储单元的内容所指示的存储单元的内容输出。输出。 din7:0 push pop clk resetDout7:0Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.
68、0.0.Copyright 2004-2011 Aspose Pty Ltd.256字节先进后出堆栈的字节先进后出堆栈的VHDL程序。程序。LIBRARY IEEE；USE IEEE.STD_LOGIC_1164.ALL；USE IEEE.STD_LOGIC_ARITH. ALL；USE IEEE.STD_LOGIC_UNSIGNED. ALL；ENTITY stack IS GENERIC (w：INTEGER: = 256; k：INTEGER: =8)； PORT (clk, reset, push, pop：IN STD_LOGIC din：IN STD_LOGIC_VECTOR (k
69、-1 DOWNTO 0)； dout：OUT STD_LOGIC_VECTOR (k-1 DOWNTO 0)； END stack；Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. ARCHI
70、TECTURE behav_stack OF stack IS TYPE memory IS ARRAY (0 TO w-1) OF STD_LOGIC_VECTOR (k-1 DOWNTO 0) ; SIGNAL ram：MEMORY； SIRNAL sp：INTEGER RANGE 0 TO w-1； BEGIN dout = ram (sp); P1: PROCESS (clk) BEGIN IF (clk EVENT AND clk = 1) THEN IF (push= 0 )THEN ram (sp ) = din； END IF； END IF； END PROCESS P1；数
71、数据据堆堆栈栈写写Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. P2: PROCESS (clk, reset) BEGIN IF (reset = 1) THEN sp= 0； ELSI
72、F (clk EVENT AND clk = 0AND push=0 ) THEN sp= sp +1； -在在clk的后沿的后沿sp+1 ElSIF (clk EVENT AND clk = 1AND pop=0 ) THEN sp= sp -1； - -sp指针修改指针修改 ENDIF； END PROCESS P2； END behav_stack； 加加减减计计数数器器操操作作Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose
73、Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.4.4 有限状态机有限状态机 有限状态机是时序电路的通用模型，任何时序电路都有限状态机是时序电路的通用模型，任何时序电路都可以表示为有限状态机。对于大部分数字电子系统，可以表示为有限状态机。对于大部分数字电子系统，都可以划分为控制单元和数据单元两个组成部分，控都可以划分为控制单元和数据单元两个组成部分，控制单元的主体是一个有限状态机，它接收外部信号和制单
74、元的主体是一个有限状态机，它接收外部信号和数据单元产生的状态的信息，产生各种控制信号，决数据单元产生的状态的信息，产生各种控制信号，决定何时进行何种数据处理。有限状态机分为两类：定何时进行何种数据处理。有限状态机分为两类：Moore型和型和Mealy型。型。 次态次态逻辑逻辑状态寄状态寄存器存器输出输出逻辑逻辑输入输入次态次态现态现态输出输出Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation onl
75、y.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.状态机的设计步骤状态机的设计步骤 定义状态机的各状态。适当地确定状态机的工作状态，定义状态机的各状态。适当地确定状态机的工作状态，是状态机设计的基础，需要充分利用设计者的设计经验。是状态机设计的基础，需要充分利用设计者的设计经验。 建立状态转换图。构造状态转换图时，通常从一个建立状态转换图。构造状态转换图时，通常从一个比较容易的状态开始。例如系统的初始状态、复位状态比较容易的状态开始。例如系统的初
76、始状态、复位状态或空闲状态等，都是很好的起始状态。为每个状态标出或空闲状态等，都是很好的起始状态。为每个状态标出转换的条件，相应的输入、输出信号。转换的条件，相应的输入、输出信号。 建立状态机进程。在建立状态机进程。在VHDL程序中，通常用进程描述程序中，通常用进程描述有限状态机。由于次态是现态及输入信号的函数，因此，有限状态机。由于次态是现态及输入信号的函数，因此，往往将现态和输入信号作为进程的敏感信号。往往将现态和输入信号作为进程的敏感信号。 进程中定义状态的转移。所有的状态均可表达为进程中定义状态的转移。所有的状态均可表达为CASE_WHEN结构中的一条结构中的一条 CASE语句，利用语
77、句，利用CASEWHEN语句语句IF_THEN_ELSE语句实现状态的转移。语句实现状态的转移。 Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.存储器控制器的设计存储器控制器的设计 存储器控
78、制器的输入信号是微处理器的就绪存储器控制器的输入信号是微处理器的就绪ready和读和读写信号写信号read_write。当上电复位或者。当上电复位或者ready有效时，存有效时，存储器控制器开始工作，并在下一个时钟周期判断本次储器控制器开始工作，并在下一个时钟周期判断本次作业任务是读存储器还是写存储器，当作业任务是读存储器还是写存储器，当read_write=1时为读操作，使时为读操作，使OE和和CS信号有效，信号有效，read_write=0时时为写操作，为写操作，WE和和CS信号有效。当信号有效。当ready信号再次有效信号再次有效时，结束本次读写操作，并使控制器返回到初始状态时，结束本次
79、读写操作，并使控制器返回到初始状态。 存储器存储器控制器控制器readyread-writeOEWECSEvaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.存储器控制器状态转移图存储器控制器状态转
80、移图 状态图状态图decisionidlewritereadreadyreadyreadyreadyreadyreadyread_writeread_writeEvaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose
81、Pty Ltd.带异步复位的双进程状态机的存储器控制器设计。带异步复位的双进程状态机的存储器控制器设计。 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL; ENTITY memoy_controller IS PORT (reset, read_write, ready, clk：IN STD_LOGIC; OE, WE,CS：OUT STD_LOGIC); END memory_controller； ARCHITECTURE state_machine OF memory_ controller IS TYPE statetype IS (idle, de
82、cision, read, write)； SIGNAL present_state, next_state：STATETYPE； Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.带异步复位的
83、双进程状态机的存储器控制器设计。带异步复位的双进程状态机的存储器控制器设计。state_comb：PROCESS (reset，present_state， read_ write，ready) BEGIN IF (reset = 1) THEN next_state= idle； OE = 0； WE = 0； CS OE= 0; WE = 0; CS = 0; IF ready = 1 THEN next_state = decision; ELSE next_state OE = 0; WE = 0; CS = 0; IF (read_write = 1) THEN next_state
84、 = read; ELSE next_state OE = 1; WE = 0; CS = 1; IF (ready = 1) THEN next_state = idle; ELSE next_state OE = 0; WE = 1; CS = 1; IF ( ready = 1) THEN next_state = idle; ELSE next_state OE=0; WE=0; CS =0; next_state=idle; END CASE; END IF; END PROCESS state_comb；Evaluation only.Created with Aspose.Sli
85、des for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd. state_clocked：PROCESS BEGIN WAIT UNTIL clk EVENT AND clk = 1； present_state = next_state； END PROCESS state_cl
86、ocked； END state_machine； PROCESS(1)CASE-WHENIF-THEN-ELSEPROCESS(2)WAIT UNTILclk EVENTAND clk=1输入输入次态次态现态现态Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.Evaluation only.Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0.Copyright 2004-2011 Aspose Pty Ltd.
