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1、Chapter 5Hardware Description Languages5.1 HDL-Based Digital Design5.1.1 Why HDLs?In previous decades, used block diagrams and schematics.Reason: lSynthesizable. lThe development of programmable logic devices and very-large-scale ASIC technology.lSynthesis tools can support much larger system design
2、s. 5.1.2 HDL Tool SuiteslText editorlCompiler lSynthesizer lSimulatorlTemplate generator lSchematic viewer lTranslatorlTiming analyzer lBack annotator5.1.3 HDL-Based Design FlowSteps in an HDL-based design flow:5.4 The Verilog Hardware Description LanguageVersion: Verilog-1995 Verilog-2001Features:l
3、Designs may be decomposed hierarchically.lEach design element has a well-defined interface and a precise functional specification.lConcurrency, timing, and clocking can all be modeled.lThe logical operation and timing behavior of a design can be simulated.5.4.1 Program StructureBasic unit of design
4、and programming: ModuleModuleDeclarationStatementEx.Verilog program for an “inhibit” gateDeclarationStatementNote: Keywords and identifier are case sensitivity.Syntax of a Verilog module declaration:Syntax of a Verilog input/output declarations:5.4.2 Logic System, Nets, Variables, and Constants1. Lo
5、gic System The possible values of a 1-bit signal: 0 Logical 0, or false 1 Logical 1, or true X An unknown logical value Z High impedance, as in three-state logicBitwise boolean operators in Verilogs logic system:2. NetsNet: Provides connectivity between modules and other elements.Verilog net types:N
6、ote: Wire is the default net type.Syntax of Verilog wire and tri net declarations:3. VariablesReg and Integer: The most commonly used.Syntax of Verilog reg and integer variable declarations:A variables value can be changed only within procedural code within a module.4. ConstantsLiteralFormat: nBdddn
7、: A decimal number that give the size of the literal in bits.B: A single letter specifying the base. b (binary), o (octal), h (hexadecimal), d (decimal)ddd: A string of one or more digits in the specified base.Parameter: Constants within a moduleSyntax of Verilog parameter declarations:5.4.3 Vectors
8、 and Operators1. Vectorreg a:b word; /* a is the leftmost bit of word, b is the rightmost bit of word. */ Ex. reg 7:0 byte1, byte2, byte3; reg 15:0 word1, word; reg 1:16 Zbus;lBit-select: bytel7, Zbus16 .lPart-select: Zbus1:8, Zbus9;16 .lConcatenation: 2b00,2b114b00112byte1,2byte2byte1, byte1, byte2
9、, byte22. OperatorsShift operators: Vacated positions filled with 0s.Arithmetic and shift operators in Verilog:Treat vectors as unsigned integers.reg signed 15:0 A;output signed 15:0 A;8bs11111111; / signed lettersEx.8b1101001138b10011000Verilog-2001: Provide for signed and unsigned arithmetic.Ex.5.
10、4.4 ArraysSyntax of Verilog array declarations:Ex.reg 7:0 byte1, recent 1:5, mem1 0:255, mem2 0:511; /* byte1: an 8-bit vector, others: arrays containing 5, 256, and 512 8-bit vectors, respectively. */ 5.4.5 Logical Operators and ExpressionsVerilog logical operators“=” and “!=” : A bit-by-bit compar
11、ison.Evaluate the truth or falsehood of each operand firstly.Ex. 4b0100&4b1011 true 4b0100&4b1011 falsePrecedencePrecedence! * / %+ - = != = !=& |&|?:The most precedenceThe lowest precedence5.4.6 Compiler Directivesinclude filenamelThe named file is read immediately and processed as if its contents
12、were part of the current file.lRead in definitions that are common to multiple modules in a project.lNesting is allowed.define identifier textlNo ending semicolon.lReplace each appearance of identifier with text.5.4.7 Structural Design ElementsThree design stylesThe corresponding current statementSt
13、ructural designInstance statementDataflow designContinuous-assignment statementBehavioral designAlways blocksThe above design styles and the corresponding statements can be intermixed within a Verilog module declaration.Verilog built-in gates:Syntax of Verilog instance statements:The first formatThe
14、 second formatThe first formatNote:lThe built-in gates can be instantiated only using the first format.lThe local expressions are listed in the same order as the ports to which theyre supposed to connect.Ex. 1 Structural Verilog program for an “inhibit” gateThe second formatNote:l Library components
15、 and user-defined modules can be instantiated with either the first or the second format.l Ports associations can be listed in any order.Logic diagram corresponding to the VrSillyXOR module:Ex. 2 Structural Verilog program for an XOR function5.4.8 Dataflow Design ElementsContinuous-assignment statem
16、ent: Describe a combinational circuit.Syntax of Verilog continuous-assignment statements:Ex. Prime-number-detector code using a conditional operator.5.4.9 Behavioral Design Elements (Procedural Code)The key element of behavioral design: always block.Syntax of Verilog always blocks:Sensitivity listNo
17、te:l When any signal in its sensitivity list changes value, always block execution.l Procedural statement in an always block execute sequentially.l All of the signals that affect the outcomes of the procedural statements should be listed.Procedural statements that are used within an always block:Blo
18、cking assignmentnonblocking assignmentbegin-end blocksifcasewhilerepeat1. Blocking and Nonblocking assignment statementslBlocking? Block the execution of subsequent procedural statements in the same always block.lNonblocking? Assign the value to the lefthand side until the entire always block has co
19、mpleted execution.Note:lAlways use blocking assignments (=) in always blocks intended to create combinational logic.lAlways use nonblocking assignments (=) in always blocks intended to create sequential logic.lDo not mix blocking and nonblocking assignments in the same always block.lDo not make assi
20、gnments to the same variable in two different always blocks.Ex. Prime-number detector using an always blockThe signal that appears on the lefthand side of an assignment statement in an always block must be declared as a reg variable.2. Begin-end blocksNote:lThe procedural statements within a begin-e
21、nd block execute sequentially.lThe begin-end block must be named when the block has its own local parameters or variables.Ex. Prime-number detector using multiple statements in an always block3. If statementEx. Prime-number detector using an if statementIf statement can be nested!4. Case statementNo
22、te: Avoid nonparallel case statement and not “all-inclusive” case.Ex. Bus-selector module using case statement5. For statementFor synthesis!Ex. Prime-number detector using a for statementCant be synthesizable!6. Repeat, while and forever statementNote:The above statements cant be used to synthesize
23、combinational logic, only sequential logic.5.4.10 Functions and Tasks1.Function: 2. Accepts a number of inputs and returns a single result. Note:l A function may not have any output or inout declarations. But it may not declare any nets or nested functions and tasks.l A function executes in zero sim
24、ulated time, and therefor cant contain any delay or other timing-related statements.l The values of any local variables are lost from one function call to the next.Ex. Verilog program for an XOR gate using an “inhibit” function 2. TaskNote: Task does not return a result.Built-in system tasks and fun
25、ctions that are used in test benches and simulation: $display, $write, $monitor, $monitoroff and $monitoron, $time, $stop.5.4.11 The Time DimensionTime delay statement: assign #real numbertimescaleSyntax: timescale time-unit / time-precisionEx. Dataflow Verilog code for a prime-number detector5.4.12
26、 Simulation1. Initializes all signals at simulation time of zero.2. Execute all the concurrent statements.How a simulator woks?Simulation cycleScan the event list Make the next scheduled assignments5.4.13 Test BenchesFunction: Specifies a sequence of inputs Initial block: Be typically used in test b
27、enches.Ex. Verilog test bench for a prime-number detector5.4.14 Verilog Features for Sequential Logic DesignEdge-triggered flip-flops:always ( posedge clock ) /positive edge of clockalways ( negedge clock ) /negative edge of clock5.4.15 SynthesisSynthesis?l Depend on the synthesis tool.l Depend on the code that write.2. Avoid the unexpected latches.1. if, else if, else if, elseEx.case statement
