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1、HCS12 Technical Training Module 5 Resets & Interrupts, Slide 1 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Resets & InterruptsHCS12 Technical Training Module
2、5 Resets & Interrupts, Slide 2 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Power-On Reset External Hardware Reset Crystal Monitor Computer Operating Properly
3、Real time interruptHCS12 Technical Training Module 5 Resets & Interrupts, Slide 3 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Power On Reset Initiated by posi
4、tive transition on VDD. 8192 E clock delay is built in to allow oscillator to stabilize. VDDCPU CLKDATA BUS/ADDRESS BUSIRESET8192 ECLK CyclesInternal Reset is held low by MCU For about 8192 E clocks In General: Subsystems and control bits are initialized to have least effect on system ( I.e. interru
5、pts masked, ports read only, serial communication disabled,.) V F P P P V - VECTOR FETCHF - FREE CYCLEP - PROGRAM FETCHFFFE FFFE 1st Opcode 2nd Opcode 3rd Opcode 128 ECLK Cycles 64 ECLK CyclesHCS12 Technical Training Module 5 Resets & Interrupts, Slide 4 MOTOROLA and the Stylized M Logo are register
6、ed in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. External & InternalResets RESET pin asserted for 2 E clocks. RESET pin must negate before reset service can begin. No delay to stabilize oscillator. 64 ECLK CY
7、CLES 32 ECLK CYCLESCPU CLK DATA BUS/ADDRESS BUS RESETIRESET 96 E ClocksSAMPLE PIN FFFE FFFE 1st Opcode 2nd Opcode3nd OpcodeHCS12 Technical Training Module 5 Resets & Interrupts, Slide 5 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service
8、names are the property of their respective owners. Motorola, Inc. 2001. Crystal Monitor (1 of 2)Useful for:1. Automatic Reset from a slow or stopped clock.2. Improves fault tolerance of system.Description:If the E clock drops below a frequency of 10 KHZ* and the Crystal Monitor function has been ena
9、bled, then:1. system reset is asserted on the external reset pin.2. Crystal Monitor vector is fetched. ElseEnter Self Clock Mode if Enabled* IF E CLOCK FREQUENCY 10KHz and 500KHz, THEN A CLOCK MONITOR RESET MAY OCCUR. ( NOT GUARANTEED ) Note: Crystal Monitor Time-out range 2usec - 150 usec.HCS12 Tec
10、hnical Training Module 5 Resets & Interrupts, Slide 6 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Crystal Monitor (2 of 2)Crystal Monitor function can be enab
11、led/ disabled at any time.PINS:1. RESET Asserted for 64 E clocks.Address Offset $0006PLLCTL - CRG PLL Control RegisterCME - Crystal Monitor Enable 1 = Monitor is enabled 0 = Monitor is disabledWhen the Crystal Monitor is enabled, a slow or stopped clocks, (including the Stop instruction) causes a cr
12、ystal failure to:1. Reset the MCU (Fetch CM Vector from $FFFC-$FFFD) or2. Enter self-clock modeHCS12 Technical Training Module 5 Resets & Interrupts, Slide 7 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of th
13、eir respective owners. Motorola, Inc. 2001. Crystal Loss/Stop & Reset Recovery Sequence CME = 1&SCME =0?MCU ResetsInterrupt? CME = 1&SCME =0?Stop ModeCount 8192 OSCLKSCME =1?Clock?Wait for ClockClocks ReleasedClock?MCU ResetsCount 8192 OSCLKClock?AssertSCM & SCMIFMCUEnters Self CMCount 8192 OSCLKClo
14、ck?Negate SCMClocks resumeNormal OperationResumeNormal OperationClock FailedStop InstructionPower-OnYesYesNoNoYesYesYesYesYesYesNoNoNoNoNoNoNote1:Crystal Monitor Timeout Range 6 - 18.5 usNote2:Self Clock Mode Frequency Range = 2.5MHZ - 5.5MHZ HCS12 Technical Training Module 5 Resets & Interrupts, Sl
15、ide 8 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Computer Operating Properly (1 of 3)Useful for:1. Insuring that the MCU does not get hung up for an extended
16、 period of time.2. Improves fault tolerance of system.Description:If the COP rate select bits are not “0” and if the watchdog timer is not reset within a specified time period:1. Then a system reset is asserted on the external reset pin.2. COP vector is fetched ( $FFFA-$FFFB )Pins: 1. Reset - Assert
17、ed for 64E clocks. HCS12 Technical Training Module 5 Resets & Interrupts, Slide 9 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Computer Operating Properly (2 o
18、f 3)PINS1. RESET Asserted for 64 E clocksARMCOP - CRG COP Arm/Reset Timer Software writes $55 followed by $AA to ARMCOP, to reset internal COP counter.Address Offset $000EAddress Offset $0008WCOP - Window COP Mode 1 = Window COP operation (Writes to ARMCOP Register must occur in the last 25% of sele
19、cted period). 0 = Normal COP operationCR2:0 - COP Watchdog Timer Rate SelectCOPCTL : Write Once in user mode, anytime in test mode. A write to COPCTL will initialize COP counter .COPCTL - CRG COP Control RegisterHCS12 Technical Training Module 5 Resets & Interrupts, Slide 10 MOTOROLA and the Stylize
20、d M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. COP Time-out Period Select (3 OF 3)COP Rate Selection Bit DefinitionTime-Out = WindowEnd = OscClkPeriod * (OscClkDivider +3) Window-Start
21、= OscClkPeriod * (0.75* OscClkDivider) + 9)CR2:0 = 000 - COP is OffOSCCLKCOP Divider ChainHCS12 Technical Training Module 5 Resets & Interrupts, Slide 11 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their
22、respective owners. Motorola, Inc. 2001. Determining Reset SourceYNYSTARTCLOCKFAILSCME=1 ?ENDNASSERTRESET PINFOR 64 E-CLOCKCYCLESCLOCKMONITORSTATUS ISLATCHEDYRESET PINNEGATION,32 E-CLOCKCYCLESALLOWEDRESETPIN STILLLOW?EXTERNALLYASSERTEDRESETGO TORESETSERVICEROUTINENGO TO COPROUTINE GO TO CRYSTAL MONIT
23、ORROUTINE RESETPIN STILL LOW ?CRYSTALMONITORSYSTEM RESET ?HCS12 Technical Training Module 5 Resets & Interrupts, Slide 12 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc
24、. 2001. INTERRUPT EXCEPTIONSINTERRUPT STACKPRIORITIESVECTORSINTERRUPT FLOWINTERRUPT INSTRUCTIONSSTANDBY MODESHCS12 Technical Training Module 5 Resets & Interrupts, Slide 13 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the
25、 property of their respective owners. Motorola, Inc. 2001. Interrupt Sources From COPFromP.I.T From Crystal MonitorCOPRESETP.I.T IRQC.MRESET INTERRUPT & RESET VECTORGENERATION & PRIORITYECT IRQSSPI IRQSSCI IRQSOther IRQSResets SWI ILLOP I_Vector X_VectorIPENDXPEND IRQ XIRQ RESETINTERNAL BUSEXTERNAL
26、BUSThe MC9S12DP256can generate over 50 Interrupt requests HCS12 Technical Training Module 5 Resets & Interrupts, Slide 14 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc
27、. 2001. Interrupt Stacking OrderSP before operationSP-9SP-8SP-6SP-4SP-2SPCCR D X Y PC xxNote: Stack operation is performed in 5-bus cycles even if SP is misaligned.When HCS12 acknowledges an interrupt, it stacks registers,then determines which vector to take. ( different from hc11 ).SP after operati
28、onHCS12 Technical Training Module 5 Resets & Interrupts, Slide 15 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Non-Maskable Exception Priority More than 40 int
29、errupt sources. Separate vector for each Reset / Interrupt source. 6 Non-Maskable sources1. RESET2. Crystal Monitor*3. COP WATCHDOG*4. TRAP5. XIRQ*6. SWI* Can generate external Reset * Once enabled, cannot be maskedHCS12 Technical Training Module 5 Resets & Interrupts, Slide 16 MOTOROLA and the Styl
30、ized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Interrupt Vector Table (1 of 3)(64 Exception Vector Entries)HCS12 Technical Training Module 5 Resets & Interrupts, Slide 17 MOTOROLA an
31、d the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Interrupt Vector Table (2 of 3)HCS12 Technical Training Module 5 Resets & Interrupts, Slide 18 MOTOROLA and the Stylized M Lo
32、go are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Interrupt Vector Table (3 of 3)HCS12 Technical Training Module 5 Resets & Interrupts, Slide 19 MOTOROLA and the Stylized M Logo are registered i
33、n the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. HCS12IRQ - Masked by I-Bit in CCRXIRQ - Masked by X-Bit in CCR*IRQEN - External IRQ Enable1 = IRQ PIN is connected to interrupt logic0 = IRQ PIN is disconnected fr
34、om interrupt logicIRQE - Interrupt Select Edge Sensitive1 = IRQ PIN is configured for negative edge0 = IRQ PIN is configured for level sensitiveINTCR - Interrupt Control RegisterWrite onceAddress Offset $001ENote: XIRQ and IRQ have internal pull-ups and enabled out of reset Pull-up can be turned off
35、 by clearing PUPEE in PUCR register Interrupt Request Pins Control* Once enabled, can not be maskedHCS12 Technical Training Module 5 Resets & Interrupts, Slide 20 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property
36、of their respective owners. Motorola, Inc. 2001. Interrupt & Priority ControlAn interrupt source can be elevated to highest priority( i.e. 7 ) by writing to HPRIO register ( bits 7 - 1 ). Interrupt priority can only be changed when I = 1 in CCRTo promote an interrupt the user writes the least signif
37、icant byte of the associated interrupt vector address to this register. If an unimplemented vector address or a non I-masked vector address (value higher than $F2) is written, then $FFF2 vector will be the default. (highest priority interrupt).HPRIO - High Priority RegisterAddress Offset $001FHCS12
38、Technical Training Module 5 Resets & Interrupts, Slide 21 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Interrupt FlowHARDWAREINTERRUPTSOFTWAREINTERRUPTMASKSET?
39、STACK MPUREGISTERCONTENTSSET I BITIN CCRLOAD INTERRUPTVECTOR INTOPROGRAM COUNTERYCONTINUE MAINPROGRAMNEXECUTE INTERRUPT SERVICE ROUTINEVECTOR TABLE$FF80$FFFFHCS12 Technical Training Module 5 Resets & Interrupts, Slide 22 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Of
40、fice. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Interrupt InstructionsMNEMONICOPERATIONSWIREGS MSP-9 SP1 IM PCM PCSPFFF6FFF7HLFUNCTIONSOFTWARE INTERRUPTRETURN FROM INTERRUPTRTIM REGS SP + 9 SPSPNote: RTI instruction will not unstack if anoth
41、er interrupt is pending.HCS12 Technical Training Module 5 Resets & Interrupts, Slide 23 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Real-Time InterruptUseful
42、for:1. Keep track of time2. Initiate tasks on periodic bases.Description:When a time-out occurs:1. Interrupt request to CPU is generated, if enabled2. RTI vector is fetched ( $FFF0-$FFF1 )HCS12 Technical Training Module 5 Resets & Interrupts, Slide 24 MOTOROLA and the Stylized M Logo are registered
43、in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Real-Time Interrupt Flow ChartSTART ASSERTINTERRUPTENDNYNYINCREMENTINTERNALCOUNTERCOUNTIS AT ANINTERVAL ?RTIF GOES to 1RTIE=1 ?HCS12 Technical Training Module 5 R
44、esets & Interrupts, Slide 25 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. Real-Time Control/Status Registers Bit 7 6 5 4 3 2 1 0Reset: 0 0 0 0 0 0 0 0RTICTL -
45、Real-Time Clock Control RegisterAddress Offset $0007RTR6:4 - Real-Time Interrupt Prescale Rate SelectRTR3:0 - Real-Time Interrupt Modulus Counter SelectOSCCLKRTI Divider ChainNote: To initialize the internal RTI counter, write to the RTICTL register.HCS12 Technical Training Module 5 Resets & Interru
46、pts, Slide 26 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. PLL Control RegistersRTIF Real Time Interrupt FlagRTIF bit is automatically set to one at the end of
47、 every RTI period.This flag can only be cleared by writing a 1. 0 = Time-out has not yet occurred. 1 = Set when the time-out period is met.CRGFLG - CRG Flag RegisterCRGINT - CRG Interrupt Enable RegisterAddress Offset $0003Address Offset $0004RTIE - Real-Time Interrupt Enable 0 = Interrupt is disabl
48、ed 1 = Interrupt is disabledHCS12 Technical Training Module 5 Resets & Interrupts, Slide 27 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001. S12 Oscillator LayoutN
49、o ground or power planes under Oscillator components, to minimise parasitics.*C6C7Oscillator componentson MCU side of board - no viasC5Good isolation of PLL / Oscillator Power supply. C5 = 1nf, C6 = 100nF.Low impedance, no vias.Optional dc blockingcapacitor goes in theEXTAL line hereC8C9C4R2C3C1C2Y1
50、Connectionto ground net/planeNo other signals should be routed near, or under the crystal components or the PLL components because these circuit nodes are very susceptible to coupled electric noise.PLL Filter cctRESET signal noise free. Dont use for external signals and / or add series filtering.* NOTE: EMCconsiderations shouldalso be taken intoconsiderationVDDRVSSRXFCVDDPLLRESETPE4VSSPLLTo 5V star point at VSSAEXTALXTALTEST
