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1、Direct current-to-direct current (DC/DC) converters with faster switching frequencies are becoming popular due to their ability to decrease the size of the output capacitor and inductor to save board space. On the other hand, the demands from the point-of-load (POL) power supply increase as processo
2、r core voltage drops below 1V, making lower voltages difficult to achieve at faster frequencies due to the lower duty cycle.Many power IC suppliers are aggressively marketing faster DC/DC converters that claim to save space. A DC/DC converter switching at 1 or 2 MHz sounds like a great idea, but the
3、re is more to understand about the impact to the power supply system than size and efficiency. Several design examples will be shown revealing the benefits and obstacles when switching at faster frequencies.Selecting an ApplicationThree different power supplies were designed and built to show the tr
4、ade offs of high switching frequency. For all three designs, the input voltage is 5V, the output voltage is 1.8V, and the output current is 3A. These requirements are typical for powering aperformance processor such as a DSP, ASIC or FPGA. To bound the filter design and performance expectations, the
5、 allowable ripple voltage is 20 mV , which is about one percent of the output voltage, and the peak-to-peak inductor current is chosen at 1A.Independent designs at frequencies of 350, 700, and 1600 kHz will be compared to illustrate the benefits and obstacles. The TPS54317, a 1.6 MHz, low-voltage, 3
6、 A synchronous-buck DC/DC converter with integrated MOSFETs was chosen as the regulator in each example. The TPS54317 from Texas Instruments features a programmable frequency, external compensation and is intended for high-density processor power point-of-load applications.Selecting the Inductor and
7、 CapacitorThe inductors and capacitors are chosen according to the following simplified formulas:Equation 1:V = L x di/dtRearranging: L Vout x (1-D)/( I x Fs)where: I = 1 A peOk-peak; D = 1.8 V/5 V=0.36Equation 2:I = C x dv/dtRearranging: C 2 x 1/(8 x Fs x V) where: V = 20 mV= 1 A peak-to-peakEquati
8、on 2 assumes a capacitor is used that has negligible series resistance, which is true for ceramic capacitors. Ceramic capacitors were chosen for all three designs because of their low resistance and small size. The multiplier of two shown above in the rearranged Equation 2 accounts for capacitance d
9、rop associated with DC bias, since this effect is not accounted for in the datasheets of most ceramic capacitors.The circuit in Figure 1 was used to evaluate the performance of each design on the bench.Figure 1: TPS54317 Reference Schematic.The components in the schematic that do not have values are
10、 the components that were modified in each design. The output filter consists of L1 and C2. The values of these components for all three designs are listed in Table 1, and were chosen based on the results from the equations above.Table 1: Capacitor and inductor selections at 350kHz, 700kHz, and 1600
11、 kHz.Note that the DC resistance of each inductor decreased as the frequency increased. This is due to less copper length needed for fewer turns. The error amplifier compensation components were designed independently for each switching frequency. The calculations for selecting the compensation valu
12、es are beyond the scope of this article.Minimum on-timeDigital converters-to-digital converter integrated circuits (IC) are characterized with a limit on the minimum controllable on-time, which is the narrowest achievable pulse width of the pulse width modulation (PWM) circuit. In a buck converter,
13、the percentage of time that the field effect transistor (FET) is on during a switching cycle is called the duty cycle, and is equal to the ratio of the output voltage to input voltage.For the converter example above, the duty cycle is 0.36 (1.8V/5.0V) and the minimum on-time of the TPS54317 is 150ns
14、 (max) as shown in the datasheet. The limit for the controllable pulse width results in a minimum achievable duty cycle, which can be easily calculated as shown in Equation 3. Once the minimum duty cycle is known, the lowest achievable output voltage can be calculated, as shown in Equation 4 and Tab
15、le 2. The lowest output voltage is also limited by the reference voltage of the converter, which is 0.9V for the TPS54317.Equation 3:Minimum duty cycle =Minimum on-time x Switching frequencyEquation 4:Minimum V out =Vin x Minimum duty cycle (bounded by TPS54317 Vref)Table 2: Minimum output voltage w
16、ith 150 ns minimumon-time.In this example, a 1.8V output(a 1.2V output ) can be generated with a 1.6 MHz switching frequency. However, if the frequency is 3MHz, the lowest possible output voltage is limited to 2.3 V and the DC/DC converter will skip pulses. The alternative is to lower the input voltage or reduce the frequency. It is a good idea to check the DC/DC converter datasheet for a guaranteed minimum controlla
