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1、打开 quartus II 软件；新建工程: 选择新建工程向导D New. . .Ctrl+N3 Open. . .Ctrl+OCloseCtrl+F4j 盘 New Proj ec t 企irard.Open Proj ect. . .Ctrl+JConvert MA+PLUS II Project.Save Froj ectClose Froiectnl SaveCtrl+SSave As.Save Ciirrent Repoi_t Secticm As.File Propertims;.Creat己匕 Updat己Expor.Convert Frogi_:amming Files.对话框
2、中介绍了其主要的功能，点击“ Next”Nev Project Vizard: IntroductionThe New Project Wizard helps you create a new project and preliminarii project settings, including the following: Project name and directory Name of the topevel design entity Project files arid libraries T arget device family and device EDA tool se
3、ttingsYou can chanqe the settinqr for an existi门口 project and specify additional project-wide settings with the Settingr command (Assignments m皂nu. You can use the various pages of the Settings dialog box to add functionality to the project.出现的对话框中说明你要建工程的存储目录，工程名称以及顶层文件名，一般情况下，工程 名称和顶层文件名相同,点击“ Nex
4、t”Hev Project Vizard: Directory,Top-Level Entity pag. | XWhat is the working directorv for this project? | E:epld verilogsrcqiaotestWhat is the name of this project?testWhat is the name of the top level design entity for this project? This name is case sensitive and must exactly match 岀e entity name
5、 in the design file.I testUse Existing Project Settings .这里让我们选择我们要加载的文件名，因为我们是新建工程，所以不需要加载任何文件，点击“ Next”Nev Project Vizard: Add Files page 2 of 5Target deviceAuto device selected by the Fitter* Specific device selected in Available devices listShow in Available device1 listSelect the family and dev
6、ice you want to target for compilation.雨 Show advanced devices 厂 Hard匚opy uomp日tible cdyAvailable devices:Name匚口忙v.LEsUFM bl.%EPM240T100A53.3V2401EPM240T100C33.3V2401,LMI接下EPM240T100C43.3V240 ,亠 ,来点击fHe/neWTverilogHDL Files创建一个程序文件。EPM240T100I53.3V2401EPM240ZM68C61.8V2401EPM240ZM68C71.8V2401EPM240ZM
7、100C61.8V2401EPM240ZM100C71.8V2401-Companion deviceHardCopy:|疋 Limit DSP 役 RAM to HardCopy device resources開%267268ab/在新建的 verilog HDL 文件中编写好所需程序，然后保存，注意文件名要和 module 后的文 件名一致，如果不一致就会导致出错。F x test.v-Sitiudule 匸est. i： ut.曰尸 .r si); input, a.rlj.r si;output u ut;not. ul (nsi _r si);and #1 u2 (sela.r a
8、, nsi); and #1 u3 (selb.rlj.r si);匸 #2 u4 (out ,r se la,r se lb); 已ndlciu clu丄已点击Start Analysis&Synthesis对编写的程序编译和纠错，如果有错误，在窗口下面会有警告, 然后回头重新修改程序，直到编译通过。耳濟兰僭觀 号卜尅監醤鞭度Start 虹Lalywiw & SynthEEiw编译通过后，出现的下面的对话框表示了我们使用的器件以及所占的器件的资源。点击 Pin Planner 可以对程序中所用的管脚和实际芯片管脚对应，设置完后关闭管脚设置 管脚设置完毕。按下图生成仿真网表Ctrl+LComp
9、ilati un ReportCmpi1er Tool! Etart CompilatiArL：alyzsCtrl+Shift+Cb 1 mill at 1 onSimul：mtiun Debug按下图S i rrnjl aT uulRadix:Bus width:V alum at1U. Uli nsAHDL Fi eED F Fi eState Machine Fi eVHDL Fi eSIJFU Builder 5r$tem一 Desi口门 FilesEl lock Di3dram/ocherridtiL： File中忑：t已iT*已|口口 HDL FileTcl Script File
10、伯il口 HDL File一 M emurir FilesH exadecimal 11 ntel-Furrridt I FileMemurH Initidlizatiun File一 VenhCdtiun/DetiLJ口口1 门口 FilesV制u已Wp已:0_Z 23N：=JT|HV：i1uh a.t18.08 nsaA 1bA 0tmtA XsiA 1卩P2山円2叭218.075 nsJDescription:Specifies the ty口已 of simulation to perform for the current Simulation focus.点击 settingEl|
11、屎/卷參|揶| 这里设置仿真的形式，为功能仿真，仿真输入选择我们上一步保存的波形GeneralJ- FilesLibrariesD eviceE-匸ip已rating Settings and 匚口门匚liti门:f：+ 匚ornpilation Process Settings+ EDA. Tool S已ttingsE- .Analiri：i：i：i： ： Synth已:示:S 已ttinqsFitter S 已ttings+ Timing .Analysis S已ttings.AssemblerD 已sign AssistantSignalTap II Logic.nalyz已 Logic .-i.rialvz曰丨门t已卄日匚已+ Simulator SettingsFowerFlav Fovxer .Analyzer S 已ttings SSN .i.nalvzer点击开始仿真按钮1 寻 匚cimpi| E t ar t E i mul at i onmm日ry出现需要的仿真结果，从结果可以看出输出 out 根据 si 的值随着 a 或 b 变化，当 si 为低电 平时out=a，当si为高电平时：out=b。
