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1、fir滤波器的Verilog程序timescale 1ns / 1ps/ Company: / Engineer:/ Create Date: 17:01:38 10/09/06/ Design Name: / Module Name: ppeifir/ Project Name: / Target Device: / Tool versions: / Description:用Verilog编写的fir滤波器程序/ Dependencies:/ / Revision:/ Revision 0.01 - File Created/ Additional Comments:/ /module f
2、irv2(clk, x, y); input clk; input 7:0 x; output 25:0 y; reg 26:0 y;reg7:0 x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16;wire21:0 acc1,acc2,acc3,acc4,acc5,acc6,acc7,acc8,acc9,acc10,acc11,acc12,acc13,acc14,acc15,acc16,acc17;reg 8:0sxin0:32;reg 5:0i,k;reg 8:0xx16:0; parameterc0=-21,c1=-8,c2
3、= 22,c3=34,c4=6,c5=-34,c6=-31,c7=32,c8=87,c9=32,c10=-154,c11=-321,c12=-217,c13=321,c14=1185,c15=1996,c16=2328; always (posedge clk)begin xx16=sxin16;for(i=0;i16;i=i+1)xxi0;k=k-1)sxink=sxink-1;sxin0=x7,x;endmult13_8 uut0(clk,c0,xx0,acc1); mult13_8 uut1(clk,c1,xx1,acc2);mult13_8 uut2(clk,c2,xx2,acc3);
4、mult13_8 uut3(clk,c3,xx3,acc4);mult13_8 uut4(clk,c4,xx4,acc5); mult13_8 uut5(clk,c5,xx5,acc6);mult13_8 uut6(clk,c6,xx6,acc7);mult13_8 uut7(clk,c7,xx7,acc8);mult13_8 uut8(clk,c8,xx8,acc9); mult13_8 uut9(clk,c9,xx9,acc10);mult13_8 uut10(clk,c10,xx10,acc11);mult13_8 uut11(clk,c11,xx11,acc12);mult13_8 u
5、ut12(clk,c12,xx12,acc13); mult13_8 uut13(clk,c13,xx13,acc14);mult13_8 uut14(clk,c14,xx14,acc15); mult13_8 uut15(clk,c15,xx15,acc16);mult13_8 uut16(clk,c16,xx16,acc17); always (posedge clk)beginy=acc161,acc161,acc161,acc161,acc161,acc16+acc171,acc171,acc171,acc171,acc171,acc17+acc151,acc151,acc151,ac
6、c151,acc151,acc15+acc141,acc141,acc141,acc141,acc141,acc14+acc131,acc131,acc131,acc131,acc131,acc13+acc121,acc121,acc121,acc121,acc121,acc12+acc111,acc111,acc111,acc111,acc111,acc11+acc101,acc101,acc101,acc101,acc101,acc10+acc91,acc91,acc91,acc91,acc91,acc9+acc81,acc81,acc81,acc81,acc81,acc8+acc71,acc71,acc71,acc71,acc71,acc7+acc61,acc61,acc61,acc61,acc61,acc6+acc51,acc51,acc51,acc51,acc51,acc5+acc41,acc41,acc41,acc41,acc41,acc4+acc31,acc31,acc31,acc31,acc31,acc3+acc21,acc21,acc21,acc21,acc21,acc2+acc11,acc11,acc11,acc11,acc11,acc1;end endmodule
