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1、EDA技术第六章 对外围硬件的访问第一节 LED一、电路结构共阴极4位LED数码管（点亮电平为高电平有效）循环点亮模式：依次点亮4个数码管，每次选通一位数码管，点亮持续一段时间后，选通下一位数码管，依次点亮一次后循环，实现循环点亮。二、VerilogHDL代码/-/ Module : led/ Filename : led.v/ Author : Wu Bin/ Date : Jul.25,2006/ Version : 1.0/ Discription: Function: 4 LED /* 注：1、pin6，8，9，12为位选择引角，低电平有效 2、采用循环点亮方式*/-timescale
2、 10ns/10nsdefine DELAY 18h3ffff/shift every 5ms（时钟50MHz）define LED 4 /LED单元数量define DIGIT1 8b01101011/udefine DIGIT2 8b11101011/odefine DIGIT3 8b01111010 /ydefine DIGIT4 8b11111111/8./-/ Module/-module led( reset, clock, led_active_in, /启动信号 led_select_out, /选择当前点亮的LED单元 led_data_out /当前点亮的LED所显示的内容
3、);/-/ Interface Declaration/- input reset; input clock; input led_active_in; output 3:0 led_select_out; output 7:0 led_data_out;/-/ Interface Declaration/- wire reset; wire clock; wire led_active_in; wire 3:0 led_select_out; wire 7:0 led_data_out;/-/ Internal Declaration/- reg 2:0 state; reg 2:0 cnt
4、; /count 4 times（4 LEDs） reg 17:0 DelayCnt;/显示delay 5ms reg 3:0 select; /显示位选择 reg 7:0 data; /显示数据/-/ Parameter Declaration/- parameter IDLE = 3h0,STAT_DISP = 3h1, /cnt计数次数判断，判断是否循环显示了一次DISP= 3h2, /数据输出送显DELAY= 3h3, /显示持续5msDISP_END= 3h4; /结束循环显示一次/-/ Main Block/- /state machine always (posedge cloc
5、k or posedge reset) begin if (reset) state = IDLE; else begin case (state) IDLE: if (led_active_in) state = STAT_DISP; STAT_DISP: begin if (cnt = LED) state = DISP_END;else state =DISP; end/先在前一状态更新cnt，再在下一状态根据cnt的值确定select和data取值 DISP: state = DELAY; DELAY: if (DelayCnt = DELAY) state = STAT_DISP;/
6、在DISP_END时才对select和data清零，使二变量在DISP和DELAY一值保持 DISP_END: state = IDLE; endcase end end /DelayCnt always (posedge clock or posedge reset) begin if (reset) DelayCnt = 0; else begin case (state) DELAY: begin if (DelayCnt = DELAY) DelayCnt = 0;else DelayCnt = DelayCnt + 1; end endcase end end /cnt always
7、 (posedge clock or posedge reset) begin if (reset)cnt = 0; else begin case (state) STAT_DISP: begin if (cnt = LED)cnt = 0;elsecnt = cnt + 1; end endcase end end /select随cnt改变而改变，选择4次（每次5ms）后清零 always (posedge clock or posedge reset) begin if (reset)select = 0; else begin case (state) IDLE:select = 0; DISP: begin case (cnt) 3h1:select = 4b0001; 3h2:select = 4b0010; 3h3:select = 4b0100; 3h4:select = 4b1000;endcase end DISP_END:select = 0; endcase end end /data：随cnt改变而改变，显示4次（每次5ms）后清零 always (posedge clock or posedge reset) begin if (reset)data =
