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1、3、 常用经典电路设计异步fifo（1）当写时钟和读时钟为同源时，定义为同步fifo； 当不同源时，定义为异步fifo。同步fifo设计较简单，异步fifo设计较难。Fifo结构形式：（2）常用Fifo可采用存储器或IP方式实现。下面主要描述异步fifo。/*/ description / asyn_fifo/*Module fifo (rst_n, wr_clk，d_in, wr_enb, rd_clk， d_out, rd_enb， empty_ind, full_ind ) ;Input rst_n ;Inpuy wr_clk， wr_enb ;Input rd_clk, rd_enb
2、;Input empty_ind, full_ind ;Input 3:0 d_in ;Output reg 3:0 d_out ; Reg 3:0 fifo_mem 15:0 ;Reg 4:0 wr_addr , rd_addr ;always ( posedge wr_clk ) begin if (rst_n) wr_addr = 5h00 ; else if (wr_enb) wr_addr = wr_addr + 1b1 ; endalways ( posedge wr_clk ) begin if (wr_enb) fifo_memwr_addr3:0 = d_in ; endal
3、ways ( posedge rd_clk ) begin if (rst_n) rd_addr = 5h00 ; else if (rd_enb) rd_addr = rd_addr + 1b1 ; endalways ( posedge rd_clk ) begin if rd_enb) d_out = fifo_memrd_addr3:0 ; end/*/reg 5:0 wr_addr_gary, wr_addr_delay1, wr_addr_delay2, wr_addr_delay3 ; assign wr_addr_gary = G (wr_addr) ; /二级制转换为格雷码a
4、lways (posedge wr_clk or negedge rst_n) begin if (rst_n) wr_addr_delay1 = 5h00 ; else wr_addr_delay1 = wr_addr_gary ; endalways (posedge rd_clk or negedge rst_n) begin if (rst_n) wr_addr_delay2 = 5h00 ; else ) wr_addr_delay2 = wr_addr_delay1 ; endassign wr_addr_delay3 = F (wr_addr_delay2) ; /格雷码转换二级
5、制wire 4:0 fifo_addr = wr_addr_delay3 rd_addr ;wire fifo_state = | fifo_addr 3:0 ;always (posedge rd_clk or negedge rst_n) begin if (rst_n) beginempty_ind = 1h1 ; full_ind = 1h0 ; endelse case fifo_addr4, fifo_state 3b00: begin / fifo is emptyempty_ind = 1h1 ; full_ind = 1h0 ; 3b01: begin / fifo is no empty and no fullempty_ind = 1h0 ; full_ind = 1h0 ; end end 3b10: begin / fifo is fullempty_ind = 1h0 ; full_ind = 1h1 ; end 3b11: begin / fifo is overflow end endEndmodule
