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1、ZZ关于模拟设计的基本考虑BasicprecautionsandtipsthatanAnalogDesignershouldknow.1.Minimumchannellengthofthetransistorshouldbefourtofivetimestheminimumfeaturesizeoftheprocess.Wedoit,tomakethelambdaofthetransistorlowi.e.therateofchangeofIdw.r.ttoVdsislow.晶体管最小沟长为工艺最小特征尺寸的4-5倍，用来减小沟长调制效应2.Presentartofanalogdesignst
2、illusesthetransistorinthesaturationregion.SooneshouldalwayskeepVgsoftheTransistor30%abovetheVt.目前模拟设计仍然是使晶体管工作在饱和区，故应使Vgs大于Vt约30%3.Oneshouldalwayssplitthebigtransistorintosmalltransistorshavingwidthorlengthfeaturesize应把大管分成小晶体管，使其宽/长特征尺寸或=15um4.W/LRatiooftransistorsofthemirrorcircuitshouldbelessthan
3、orequalto5,toensurethepropermatchingofthetransistorsinthelayout.Otherwise,itresultstotheSystamaticOffsetinthecircuit.电流镜电路的晶体管的w/l比应小于或等于5，以保证较好的Matching,否则会有系统失调5.Oneshouldmakealltherequiredpinsintheschmeticbeforegeneratingthelayoutview.Becauseitsdiffculttoaddapininthelayoutview.AllIOpinsshouldbeam
4、etal2pinswhereasVddandGroundshouldbemetal1pins在电路中画出所有的管脚（pin），之后才作layout。因为在layout中增加一个pin是比较困难的。所有的IOpin应该用metal2pin，Vdd和GND用metal1pin6.Oneshouldfirstsimulatethecircuitwiththetypicalmodelparametersofthedevices.SinceVtofthetrasistorcanbeanythingbetweenVt(Typical)-/+20%.Sowecheckourcircuitfortheextr
5、emecasesi.e.Vt+20%,Vt-20%.AtransistorhavingVt-20%iscalledafasttransistorandtransistorhavingVt+20%iscalledslowtransistor.Itsjustawaytodifferentiatethem.Sowiththesefastandslowtransistormodelswemakefourcombinationcallednfpf,nfps,nspf,nsps,whichareknownasprocesscorners.Now,oncewearesatisfiedwiththecircu
6、itperformancewithtypicalmodelsthanwecheckitindifferentprocesscorners,totaketheprocessvariationintoaccount.Vtisjustoneexampleoftheprocessvariationthereareothersparametertoo.首先先用tt做电路仿真。考虑Vt有+20%(slow)和-20%(fast),需要对工艺角考虑，FF，SS，FS，SF。除Vt，其他工艺参数也会有变化7.Itsthumbrulethatpolyresistancehasa20%processvariati
7、onwhereaswellresistancehasgot10%.ButthepolyresistancehasgotlowertemperaturecoefficentandlowerSheetResistancethanwellresistanceSowechoosetheresistancetypedependingupontherequirments.PolyCapacitancehasgotaprocessvariationof10%.多晶硅电阻大约有20%的工艺变化，而阱区电阻变化约为10%。但多晶硅电阻有较低的温度系数和低的方块电阻，应根据需要来选择电阻。多晶硅电容约有10%工艺
8、变化8.Oneshouldalsocheckthecircuitperformancewiththetemperaturevariation.Weusulydoitfortherangeof-40Cto85C.需考虑温度变化对电路性能的影响，通常在-40C到85C范围9.Oneshouldtaketheparasiticcapacitanceintoaccountwhereveroneismakinganoverlapwithmetallayersorwells.有覆盖金属层或阱区时，须考虑寄生电容10.InLayout,alltransistorsshouldbeplacedinonedir
9、ection,toprovidethesameenvironmenttoallthetransistors.Layout中，所有晶体管统一摆放方向，使有相同的环境11.Oneshouldplacealltransistorinlayoutwithaduecaretothepinpositionbeforestartroutingthem.在对晶体管布局布线之前，考虑Pin的位置12.OneshouldalwaysusetheMetal1forhorizontalroutingandMetal2fortheverticalroutingasfaraspossible.尽量使用metal1横向布线
10、，metal纵向布线13.OneshouldneverusePOLYasroutinglayerwhentheinterconnectscarriesacurrent.Onecanhaveashortgateconnectionusingpoly.在互连用来传送电流时，不要用Poly来做互连。可以用poly做短的栅连接。14.Oneshouldtrytoavoidrunningmetaloverpolygate.Asthiscausetoincreaseinparasiticcapacitance.避免金属在多晶硅栅上走线，会增加寄生电容15.Currentinallthetransistor
11、andresistorpartshouldflowinthesamedirection所有晶体管和电阻有相同的电流走向16.OneshoulddothePower(Vdd&Gnd)routingintoplayermetal(metal5only).BecauseToplayermetalsareusuallythickerandwiderandsohaslowresistance.在最上层金属做电源（Vdd和GND）布线。因为最上层金属通常更厚、更宽，因而电阻较小17.Oneshouldalwaysmergedrainandsourceoftransistor(ofsametype)conn
12、ectedtogether.merge连接的Source和Drain18.TominimizetheprocessvariationintheResistorvalueoneshouldalwaystaketheresistorswidththreetofourtimesofthedefaultvalue.wedoittodecreasethevalueofdifferentialofR(L)为减小工艺变化对电阻影响，应使电阻的宽度为默认值的3-4倍19.Oneshouldcovertheresistancewithmetallayer,toavoidthedamagedduringthewa
13、ferleveltesting.用金属覆盖电阻，避免wafer级测试时的损伤20.OneshouldalwaysmakeaCommonCentroidstructureforthematchedtransistorinthelayout.Eachdifferentialpairtransistorshouldbedivideintofourtransistorsandshouldbeplacedintworowscommoncentroidstructure.Onemayusethethelinearcommoncentroidstructureforthecurrentmirrorcircuit.对匹配的晶体管用共中心的结构差分对管，分割为4管，2*2排列，共中心对电流镜，可用线形共中心21.Itsadvisiabletoputadummylayersaroundtheresistanceandthecapacitancetoavoidtheerosionatthetimeofetching.建议在电阻和电容周围作dummy22.OneshouldalwayshaveaGuardRingarroundthedifferentialpair.在差分对周围作保护环23.AlwaysputaGuardRingarroundtheN-wellandP-well.在N阱和P阱作保护环
