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1、.设计一个“01111110”序列检测器，采用VHDL语言编写。2.设计一4-2编码器（10分）3.设计一异步复位、模60计数器（10分）4.试编写“01111110”序列发生器的VHDL语言程序。5.采用VHDL语言描述该电路6.编写16选1数据选择器的VHDL源程序。设电路的16位数据输入为A15.0，使能控制端为ENA，高电平有效，数据选择输出为Y。7.编写8位二进制数据比较器的VHDL源程序。设电路的两个8位二进制输入为A7.0和B7.0，当A7.0B7.0是时输出GT=1, 当A7.0B7.0是时输出LT=1, 当A7.0=B7.0是时输出EQ=1。8.采用VHDL语言描述该电路。9
2、.下表为双向数据缓冲器的功能表，根据该功能表采用VHDL语言编写双向数据缓冲器（a位宽8）。EnDr功能00a=b01b=a1X三态10.采用VHDL语言描述该电路11.编写程序（10分） 试编写上升沿触发的D触发器的VHDL语言程序。12.编写程序（10分）试编写下降沿触发的D触发器的VHDL语言程序。答案1.library IEEE;use IEEE.STD_LOGIC_1164.all;entity rplcont is port( clk,rst,datain : in STD_LOGIC; q : out STD_LOGIC); end rplcont;architecture rp
3、lcont of rplcont istype states is (st0,st1,st2,st3,st4,st5,st6,st7,st8);signal cur_state,next_state : states;beginprocess(clk,rst)begin if rst=1 then cur_state=st0; elsif clkevent and clk=1 then cur_state=next_state; end if; end process;process(cur_state,next_state) begin q if datain=0 then next_sta
4、te=st1; else next_state if datain=1 then next_state=st2; else next_state if datain=1 then next_state=st3; else next_state if datain=1 then next_state=st4; else next_stateif datain=1 then next_state=st5; else next_stateif datain=1 then next_state=st6; else next_stateif datain=1 then next_state=st7; e
5、lse next_stateif datain=0 then next_state=st8; q=1; else next_state if datain=0 then next_state=st1; else next_state=st2; end if; end case;end process; end rplcont;2.设计一4-2编码器（10分）library ieee;use ieee.std_logic_1164.all;entity code4 is port( a,b,c,d : in std_logic; y0,y1 : out std_logic );end code4
6、;architecture code4 of code4 issignal ddd:std_logic_vector(3 downto 0); signal q:std_logic_vector(1 downto 0);beginddd=a&b&c&d;process(d)begin if (ddd(0)=0) then q = 11; elsif (ddd(1)=0) then q = 10; elsif(ddd(2)=0) then q=01; else q = 00;end if;end process;y1=q(0);y0=q(1);end code4;3.设计一异步复位、模60计数器
7、（10分）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt60 is port( clk,rst : in std_logic; m60 : out std_logic_vector(5 downto 0) );end cnt60;architecture cnt60 of cnt60 issignal cnt60:std_logic_vector(5 downto 0); beginprocess(clk,rst)begin if rst=1 then cnt600); el
8、sif clkevent and clk=1 then if cnt60=59 then cnt600); else cnt60= cnt60+1; end if;end if;end process;m60=cnt60;end cnt60;4. library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_unsigned.all;entity rplcont is port( clk,rst : in STD_LOGIC; zo : out STD_LOGIC); end rplcont;architecture rplcont o
9、f rplcont issignal count:std_logic_vector(2 downto 0);signal z:std_logic;beginprocess(clk,rst) begin if rst=1 then count=000; elsif clkevent and clk=1 then if count=7 then count=000; else countzzzzzzzz=0; end case; end process; process(rst,clk) begin if rst=1 then zo=0; elsif clkevent and clk=1 then
10、 zo=z; end if; end process; end rplcont;5.程序如下library IEEE;use IEEE.STD_LOGIC_1164.all;entity rplcont is port( clk : in STD_LOGIC; count : out STD_LOGIC_VECTOR(7 downto 0); end rplcont;architecture rplcont of rplcont issignal count_in_bar:std_logic_vector(7 downto 0);component dffport (clk,d:in std_logic; q,qb:out std_logic);end component ;begin count_in_bar(0)count_in_bar(i), d=count_in_bar(i+1), q=count(i),qb=count_in_bar(i+1); end generate;end rplcont;6.程序如下library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux16_1 isport( s3,s2,s1,s0: in std_logic;d
