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1、毕业设计说明书基于VHDL语言的8位RISC-CPU的设计学院：专业：学生姓名：学号：指导教师：2011年5月ARISCDesign:SynthesisoftheMIPSProcessorCoreA full die photograph of the MIPS R2000 RISC Microprocessor is shown above. The 1986 MIPS R2000 with five pipeline stages and 450,000 transistors was the world fsrst commercial RISC microprocessor. Phot
2、ograph ?1995-2004 courtesy of Michael Davidson, Florida State UniversityJimrm.-i I 不广封*SA14.1TheMIPSInstructionSetandProcessorTheMIPSisanexampleofamodernreducedinstructionsetcomputer(RISC)developedinthe1980s.TheMIPSinstructionsetisusedbyNEC,Nintendo,Motorola,Sony,andlicensedforusebynumerousothersemi
3、conductormanufacturers.Ithasfixed-length32-bitinstructionsandthirty-two32-bitgeneral-purposeregisters.Register0alwayscontainsthevalue0.Amemorywordis32bitswide.AsseeninTable14.1,theMIPShasonlythreeinstructionformats.OnlyI-formatLOADandSTOREinstructionsreferencememoryoperands.R-formatinstructionssucha
4、sADD,AND,andORperformoperationsonlyondataintheregisters.Theyrequiretworegisteroperands,RsandRt.Theresultoftheoperationisstoredinathirdregister,Rd.R-formatshiftandfunctionfieldsareusedasanextendedopcodefield.J-formatinstructionsincludethejumpinstructions.Table 14.1 MIPS32-bitInstructionFormatsFieldSi
5、ze6-bits5-bits5-bits5-bits5-bit$6-bitsR-FormatOpcodeRsRtRdShiftFunction1-FormatOpcodeRs一RtAddress/immedialevalueJ-FormatOpcodeBranchtargetaddressLWisthemnemonicfortheLoadWordinstructionandSWisthemnemonicforStoreWord.ThefollowingMIPSassemblylanguageprogramcomputesA=B+C.LW$2,B;Register2=valueofmemorya
6、taddressBLW$3,C;Register3=valueofmemoryataddressCADD$4,$2,$3;Register4=B+CSW$4,A;ValueofmemoryataddressA=Register4TheMIPSI-formatinstruction,BEQ,branchesiftworegistershavethesamevalue.Asanexample,theinstructionBEQ$1,$2,LABELjumpstoLABELifregister1equalsregister2.Abranchinstructionaddsessfieldcontain
7、stheoffsetfromthecurrentaddress.ThePCmustbeaddedtotheaddressfieldtocomputethebranchaddress.ThisiscalledPC-relativeaddressing.LWandSWinstructionscontainanoffsetandabaseregisterthatareusedforarrayaddressing.Asanexample,LW$1,100($2)addsanoffsetof100tothecontentsofregister2andusesthesumasthememoryaddres
8、storeaddatafrom.Thevaluefrommemoryisthenloadedintoregister1.Usingregister0,whichalwayscontainsa0,asthebaseregisterdisablesthisaddressingfeature.Table 14.2 MIPSProcessorCoreInstructionsMnemonicFormatOpcodeFieldFunctionFieldInstructionAddR032AddAddi18-AddlimmediateAdduR033AddUnsignedSubR034SubtractSub
9、uR035SubtractUnsignedAndR036BitwiseAndOrR0137BitwiseORSilR00ShiftLeftLogicalSrlR02ShiftRightLogical8ltR042SetifLessThanLui115-LoadUpperImmediateLw135-LoadWordSw143StoreWordBeq14-BramchonEqualBns5-BranchonNotEqualJJ2-JumpJalJ3-JumpandLink(usedforCall)JrR08JumpRegister(usedforReturn)Asummaryofthebasic
10、MIPSinstructionsisshowninTable14.2.IndepthexplanationsofallMIPSinstructionsandassemblylanguageprogrammingexamplescanbefoundinthereferenceslistedinsection14.11.AhardwareimplementationoftheMIPSprocessorcorebasedontheexampleinthewidelyusedtextbook,ComputerOrganizationandDesignTheHardwareSoftwareInterfa
11、cebyPattersonandHennessy,isshowninFigure14.1.ThisimplementationoftheMIPSperformsfetch,decode,andexecuteinoneclockcycle.StartingattheleftinFigure14.1,theprogramcounter(PC)isusedtofetchthenextaddressininstructionmemory.Sincememoryisbyteaddressable,fourisaddedtoaddressthenext32-bit(or4-byte)wordinmemor
12、y.Atthesametimeastheinstructionfetch,theadderaboveinstructionmemoryisusedtoaddfourtothePCtogeneratethenextaddress.Theoutputofinstructionmemoryisthenext32-bitinstruction.TheinstructionsopcodeisthensenttothecontrolunitandthefunctioncodeissenttotheALUcontrolunit.Theinstructionregisteraddressfieldsareus
13、edtoaddressthetwo-portregisterfile.Thetwo-portregisterfilecanperformtwoindependentreadsandonewriteinoneclockcycle.Thisimplementsthedecodeoperation.4frar jc:d- ：3b2aADD A.DD InstruelionMemoryPee dI MFuCl A：3i-0|Oontrcll*s：r_:l =-mr -ub75-51jCior；20-1&Rud月苗15 t三rRend二二”三，R由d口啊 !ltr2D-ata M emeryMu电独Re
14、ac 0fll9Inaf jcton曰nebMamWritflALUSre Rac；-恒-sf jcton?i3in 4ENtend/ALUALLI R白-i胃”Da：aCflntrnlFigure14.1MIPSSingleClockCycleImplementationThetwooutputsoftheregisterfilethenfeedintothedataALUinputs.ThecontrolunitssetuptheALUoperationrequiredtoexecutetheinstruction.Next,LoadandStoreinstructionsreadorwr
15、itetodatamemory.R-formatinstructionsbypassdatamemoryusingamultiplexer.Last,R-formatandLoadinstructionswritebackanewvalueintotheregisterfile.PC-relativebranchinstructionsusetheadderandmultiplexershownabovethedataALUinFigure14.1tocomputethebranchaddress.Themultiplexerisrequiredforconditionalbranchoperations.Afteralloutputshavestabilized,thenextclockloadsinthenewvalueofthePCandtheprocessrepeatsfort
