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1、大学HUNAN UNIVERSITY 硬件根底实验2 实验报告一、 实验预习 1.书中的图形实现微程序控制器，中间的映射逻辑终究是怎么实现的？ 答：但出现分支时，预设端信号由IR决定。IR为1时信号有效，输出为1. 通过IR的值映射为下址的低三位，从而产生下址。 2.书中设计用到了强写强读，为什么要设计这个功能？ 答：满足用户因为没有初始化mif文件时输入数据的需要。二、 实验目的 微程序控制器实验的主要任务：生成CPU里的控制信号，并使程序按正 确的顺序执行。核心局部是ROM，存放机器指令的微程序。 1、掌握微程序控制器的组成、工作原理； 2、掌握微程序控制器的根本概念和术语：微命令、微操作
2、、微指令、微 程序等； 3、掌握微指令、微程序的设计与调试方法； 4、通过单步运行假设干条微指令，深入理解微程序控制器的工作原理；二、实验电路 图1附：电路图过大，请放大观察详情三、实验原理 将机器指令的操作从取指到执行分解为假设干个更根本的微操作序列，并将有 关的控制信息微命令以微码的形式编成微指令输入到控制存储器中。这样， 每条机器指令将与一段微程序对应，取出微指令就产生微命令，以实现机器指令 要求的信息传送与加工。四、实验步骤与概述 1)设计状态机局部 a、编写VHDL代码如下LIBRARY ieee;ENTITY zhuangtaiji IS PORT ( reset : IN STD
3、_LOGIC := 0; clock : IN STD_LOGIC; qd : IN STD_LOGIC := 0; dp : IN STD_LOGIC := 0; tj : IN STD_LOGIC := 0; t1 : OUT STD_LOGIC; t2 : OUT STD_LOGIC; t3 : OUT STD_LOGIC; t4 : OUT STD_LOGIC );END zhuangtaiji;ARCHITECTURE BEHAVIOR OF zhuangtaiji IS TYPE type_fstate IS (idle,st1,s_st2,st4,st2,st3,s_st4,s_
4、st3); SIGNAL fstate : type_fstate; SIGNAL reg_fstate : type_fstate;BEGIN PROCESS (clock,reset,reg_fstate) BEGIN IF (reset=1) THEN fstate = idle; ELSIF (clock=1 AND clockevent) THEN fstate = reg_fstate; END IF; END PROCESS; PROCESS (fstate,qd,dp,tj) BEGIN t1 = 0; t2 = 0; t3 = 0; t4 IF (NOT(qd = 1) TH
5、EN reg_fstate = st1; ELSE reg_fstate = idle; END IF; t1 = 0; t2 = 0; t3 = 0; t4 IF (tj = 1) AND NOT(dp = 1) THEN reg_fstate = st1; ELSIF (dp = 1) AND NOT(tj = 1) THEN reg_fstate = s_st2; ELSE reg_fstate = st2; END IF; t1 = 1; t2 = 0; t3 = 0; t4 IF (tj = 1) THEN reg_fstate = s_st2; ELSE reg_fstate =
6、s_st3; END IF; t1 = 0; t2 = 1; t3 = 0; t4 IF (tj = 1) AND NOT(dp = 1) THEN reg_fstate = st4; ELSIF (dp = 1) AND NOT(tj = 1) THEN reg_fstate = idle; ELSE reg_fstate = st1; END IF; t1 = 0; t2 = 0; t3 = 0; t4 IF (tj = 1) AND NOT(dp = 1) THEN reg_fstate = st2; ELSIF (dp = 1) AND NOT(tj = 1) THEN reg_fst
7、ate = s_st3; ELSE reg_fstate = st3; END IF; t1 = 0; t2 = 1; t3 = 0; t4 IF (tj = 1) AND NOT(dp = 1) THEN reg_fstate = st3; ELSIF (dp = 1) AND NOT(tj = 1) THEN reg_fstate = s_st4; ELSE reg_fstate = st4; END IF; t1 = 0; t2 = 0; t3 = 1; t4 IF (tj = 1) THEN reg_fstate = s_st4; ELSE reg_fstate = idle; END IF; t1 = 0; t2 = 0; t3 = 0; t4 IF (tj = 1) THEN reg_fstate = s_st3; ELSE reg_fstate = s_st4; END IF; t1 = 0; t2 = 0; t3 = 1; t4 t1 = X; t2 = X; t3 = X; t4 = X; report Reach undefined state; END CASE; END PROCESS;END BEHAVIOR; b、新建block file选定zhaungtaiji得到电路图2)设计rom局部 a、编写V
