《位乘法器学习笔记Verilog语言源程序仿真程序》由会员分享,可在线阅读,更多相关《位乘法器学习笔记Verilog语言源程序仿真程序(18页珍藏版)》请在金锄头文库上搜索。
1、LCD1602显示源程序如下:module lcd1602(input clk, /60M input rst_n, output lcd_p, /Backlight Source + lcd屏幕背光 output lcd_n, /Backlight Source - output reg lcd_rs, /0:write order; 1:write data output lcd_rw, /0:write data; 1:read data output reg lcd_en, /negedge 在lcd_en下降沿需保证数据有效 output reg 7:0 lcd_data); mux
2、16 mul(.rst_n(rst_n),.clk(clk),.start(start),.ain(data0),.bin(data1),.yout(data2),.done(done);/端口名称关联 /-lcd1602 order-parameter Mode_Set = 8h31, /功能设立, Cursor_Set = 8h0c, /光标设立 Address_Set = 8h06, /输入模式设立 Clear_Set = 8h01; /清屏设立 /*LCD1602 Display Data*/ wire 7:0 data_r0,data_r1,data_r2; /乘数、被乘数wire
3、15:0data0,data1; /结果显示wire 31:0data2; wire 7:0 addr; /write addresswire start,done; assign data_r0 = 8h30 + data07:0 ; / 8h30在LCD1602上显示值为0。 assign data_r1 = 8h30 + data17:0 ;assign data_r2 = 8h30 + data27:0;/-address-assign addr = 8h80; /*LCD1602 Driver*/ /-lcd1602 clk_en-reg 31:0 cnt;reg lcd_clk_e
4、n;always (posedge clk or negedge rst_n) begin if(!rst_n) begin cnt = 1b0; lcd_clk_en = 1b0; end else if(cnt = 32h24999) /600us begin lcd_clk_en = 1b1; cnt = 1b0; end else begin cnt = cnt + 1b1; lcd_clk_en = 1b0; endend /-lcd1602 display state-reg 6:0 state;always(posedge clk or negedge rst_n)begin i
5、f(!rst_n) begin state = 1b0; lcd_rs = 1b0; lcd_en = 1b0; lcd_data = 1b0; end else if(lcd_clk_en) begin case(state) /-init_state- 6d0: begin lcd_rs = 1b0; lcd_en = 1b1; lcd_data = Mode_Set; /进入功能设立模式,“31”:数据总线8位,显示一行。6*7点阵/每字符 state = state + 1d1; end 6d1: begin lcd_en = 1b0; /lcd_en变低电平,使led_en出现下降沿
6、 state = state + 1d1; end 6d2: begin lcd_rs = 1b0; lcd_en = 1b1; lcd_data = Cursor_Set;/光标设立:光标右移一格,且AC值加1. state = state + 1d1; end 6d3: begin lcd_en = 1b0; state = state + 1d1; end 6d4: begin lcd_rs = 1b0; lcd_en = 1b1; lcd_data = Address_Set;/模式设立:写入新数据后光标右移,AC自增1 state = state + 1d1; end 6d5: be
7、gin lcd_en = 1b0; state = state + 1d1; end 6d6: begin lcd_rs = 1b0; lcd_en = 1b1; lcd_data = Clear_Set;/清屏操作:0x01 state = state + 1d1; end 6d7: begin lcd_en = 1b0; state = state + 1d1; end /-work state- 6d8: begin lcd_rs = 1b0; lcd_en = 1b1; lcd_data = addr; /write addr state = state + 1d1; end 6d9: begin lcd_en = 1b0; state = state + 1d1; end 6d10: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = R; /write data state = state + 1d1; end 6d11: begin lcd_en = 1b0; state = state + 1d1; end 6d12: begin