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1、LIBRARY IEEE; -正弦信号发生器源文件USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;LIBRARY my;USE my.my_rom.ALL;ENTITY SINGT IS PORT ( CLK : IN STD_LOGIC; -信号源时钟 DOUT : OUT STD_LOGIC_VECTOR (rom_width-1) DOWNTO 0) );-8位波形数据输出END;ARCHITECTURE behav OF SINGT ISSIGNAL i:integer range 0 to (adr_high-1
2、):=0;-设定内部节点作为地址计数器BEGIN PROCESS(CLK) BEGIN if CLKevent and CLK=1 then if i = (adr_high-1) THEN i = 0; ELSE i = i + 1; END IF; end if;dout = my_rom(i); END PROCESS;END behav;LIBRARY IEEE; -正弦信号发生器源文件USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;PACKAGE my_rom ISCONSTANT rom_width : POS
3、ITIVE := 8;CONSTANT adr_high : POSITIVE := 64;SUBTYPE rom_word IS STD_LOGIC_VECTOR(rom_width-1) DOWNTO 0); TYPE rom_table IS ARRAY(0 TO (adr_high-1) OF rom_word;CONSTANT my_rom:rom_table:= ( 11111111,11111110,11111100,11111001,11110101,11101111,11101001,11100001, -00-0f 11011001,11001111,11000101,10
4、111010,10101110,10100010,10010110,10001001, - 01111100,01110000,01100011,01010111,01001011,01000000,00110101,00101011, -10-1f 00100010,00011010,00010011,00001101,00001000,00000100,00000001,00000000, -00000000,00000001,00000100,00001000,00001101,00010011,00011010,00100010, -20-2f00101011,00110101,01000000,01001011,01010111,01100011,01110000,01111100, -10001001,10010110,10100010,10101110,10111010,11000101,11001111,11011001, -30-3f 11100001,11101001,11101111,11110101,11111001,11111100,11111110,11111111 );-END;
