《先进芯片封装知识介绍.》由会员分享，可在线阅读，更多相关《先进芯片封装知识介绍.（22页珍藏版）》请在金锄头文库上搜索。
1、Advaneed Packaging TechOutline Package Development Trend 3D Package WLCSP & Flip Chip PackagePackage Development Trend90 nmMoore Law2nd GenerationBGA / Fan-In PoP二二二二二二二PPonturi；SOPCOL QfHCu PillarCu WireHybrid SiPBD sUcklAodulePiP&PbPSBS aWLP3D aWLPWLCSP/iCSP Std.M O W kJ tZv* V* V Lf W/ TSV mterwe
2、r45 / 40 nm 32 / 28 nmwire bondPac-aee3rd GenerationFC & 3D SiP & Innovation PkgLKLfLF ELKricePBGAcost performance1984199040nm28 nm 1 PlatingaWLPOieFBGA _MCP . Stacked Die FCKCM Hybrid FOWB MocXjIc System IntegrationPoP3 DeDttcrcU200020082009201020112012COL- VSOP(2 dies) DOVSOPCOL- VSOP(2 dies) DOVS
3、OPPackage Development TrendCOL- VSOP(2 dies) DOVSOPCOL- VSOP(2 dies) DOVSOP SO Family QFP Family BGA FamilyCOL- VSOP(2 dies) DOVSOPCOL- VSOP(2 dies) DOVSOPTSOPEDHS.BGA MPBGAPOPBGADHSQfPEW1S-QFPLQFPFCBGACOL-TSOP (4 dies) COL TSOP (8 di) Balance moldUn-balanco moldDHSXQFPE-PAD LQFPEHS-FCBGA MP4：CBGA T
4、erminator FCBGAVSOPTQFPVQFPEBGACOL- VSOP(2 dies) DOVSOPPackage Development Trend CSP Family Memory Card SiP ModuleMini SD Micro SD RSMMC MMC MCfOWin *BT ModuloTFBGAS-TFBGA WUM丿XFBGA COSBGA1WLC5PKDWimax ModuleGPS ModuleWiFi BT $ FM Radio Module3D Package3D Package3D Package Introduction8HietCSP 4- S-
5、CSPPackage onPackage (PoP)Stacki ngUOQe蚩 u- -euoloun 亠Multi ChipStacketCSP Stack3 S CSP4SS-SCSPSSCSP2 Chip Stack Flip Chip & Wirebond2 Chip Stack WirebondUltra thin StackStacked DieProcess flow of FOW and Film Spacer If FOW spacer is applied to same oizc die attach/ the film spacer cut & place machi
6、ne(modulc) is not required, UPH can be inreased, and wire bond ability for top die will be improved by supported wire bonding area(no die overhang).device attachCurrvnt same size die atUch nMhod Wth film spacerFilm spacer attachb b 6 du bbBottom die :Top die : 3SOrOOx3mlFOW materilBottom dieNew same
7、 size attach method vMth FOW spacerTSV TSV (Through Silicon Via)A through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSV technology is imports nt in creating 3D packages and 3D integrated circuits A3D package (System in Package, Chi
8、p Stack MCMZ etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less spaceIn most 3D packages, the stacked chips are wired together along their edges This edge wiring slightly increases the length and width of the package and usually requires an extra inter
9、poser* layer between the chips.In some new 3D packages, through-silicon via replace edge wiring by creating vertical connections through the body of the chips The resulting package has no acded length or thicknessWire Bonding Stacked DiePOP Whats PoP? PoP is Package on PackageTop and bottom packages
10、 are tested separately by device manufacturer or subcon.Logic package Assembly & TestMemory package Assembly & TestPoP PoP Core Tech no logyPin Gate MoldWafer ThinningPoP AmkorzsTMV PoPAllows for warpage reduction by utilizing fully-molded structure More compatible with substrate thickness reduction
11、 Provides fine pitch top package interface with thru mold via Improved board level reliability Larger die size / package size ratio Compatible with flip chip, wire bond, or stacked die configurations Cost effective compared to alternative next generation solutionsTMV PoP Cross SectionsThrough Mold V
12、ia1Top viewBottom viewB2PoP Process Flow of TMV PoPBall Placement on top surfaceDie BondI Laser drillingLaser beamThermal effectBall Placement on bottomSingulation Final Visual InspectionBase Mtlp* Memory die Analog die Digital die Digital(Btm die) + Analog(Middle die) + Memory(Top pkg) Potable Digi
13、tal Gadget Cellular Phone, Digital St川 Camera, Potable Game Unit Why PiP?/Easy system integrationFlexible memory configuration丁 100% memory KGD/Thinner package than POPHigh IO interconnection than POPi 丁Small footprint in CSP format)丨“ il * IU IIOO OO CJIt has standard ball size and pitch PiP Core Tech no logyConstructed with: Film Adhesive die attach Epoxy paste for Top PKG Au wire bonding for interconnction Mold encapsulationWafer ThinningPiP PiP-W/B PiPand FC PiPWB PIPFC PIPWLCSP & Flip Chip PackageWLCSP What is WLCSP?WLCSP
