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1、1.IEEE 754 format of X is (41360000)16, what is its decimal value?将十六进制数展开，可得二进制数格式为：0 100 0001 0 011 0110 0000 0000 0000 0000指数 e=阶码一127=1000001001111111= 00000011 =(3) 10包括隐藏位 1 的尾数 1.M = 1.011 0110 0000 0000 0000 0000 = 1.011011于是有：X = (-1)s * 1.M * 2e = +(1.011011)2 * 23 = + (1011.011)2 = (11.37
2、5)102.Let the carry bits of an adder are C 4, C3, C2, C1. C0 is the carry from the low bit. Please give the logic expressions of C4, C3, C2, C1 in ripple carry mode and carry look ahead mode respectively.(1) 串行进位G1 = A1B1 , P1 = A1 B1G2 = A2B2 , P2 = A2 B2G3 = A3B3 , P3 = A3 B3G4 = A4B4 , P4 = A4 B4
3、C1 = G1 + P1P0C2 = G2 + P2C1C3 = G3 + P3C2C4 = G4 + P4C3(2) 并行进位C1 = G1 + P1C0C2 = G2 + P2G1 + P2P1C0C3 = G3 + P3G2 + P3P2G1 + P3P2P1C0G4 = G4 + P4G3 + P4G3G2 + P4P3P2G1 + P4P3P2P1C03.Suppose a computer with a clock frequency of 100 MHz as four types of instructions, and the frequency of usage and t
4、he CPI for each of them are given in table.Instruction operationFrequency of usageCycles per instructionArithmetic-logic40%2Load/store30%4compare8%2.5branch22%3(1) Find the MIPS of the computer and the T (CPU time) required to run a program of 107 instructions.(2) Combining comparing and branch inst
5、ructions together so that compare instructions can be replaced and removed. Suppose each compare instruction was originally used with one branch instruction, and now each branch instruction is changed to a compare&branch instruction. Also suppose that the new proposal would decrease the clock freque
6、ncy by 5%, because the new compare&branch instruction needs more time to execute. Find the new CPIave, MIPS, and T.CPIave = (0.4*2+0.*4+0.22*3)/0.92 = 2.9MIPS = f(MHz)/CPIave = (100*0.95)/2.9 = 32.76T = IC CPIave/f(Hz) = ( 0.92*10000000) *2.9/( 0.95*100*1000000)= 0.28s4 CPU has 16 address bus lines
7、(A 15-A0), 8 data bus lines (D 7-D0), R/W (high level represents Read, while low level represents Write), MREQ control line for accessing memory (low level represents accessible).Memory space allocation: The minimal 8K are used for system program, which is composed of Read Only Memory chip; the foll
8、owing 24K are used for user program; the last 2K are used for system working.Now we have: EPROM 8K * 8 (contains CS control line only);SRAM 16K*1, 2K*8, 4K*8, 8K*8;Decoder 74LS138;and other logic gatesQuestions:(1) Select appropriate chips to form the required memory space. Which chips are needed? H
9、ow many chips are needed? Descript the corresponding data bus length, address bus length and control bus line.(2) Descript the address distribution of memory.(3) Descript select chip logic functions (片选逻辑函数) of each chip.(4) Descript the connection way among CPU, memory chips and 74LS138.解：(1)根据给定条件
10、，选用EPROM： 8Kx8位芯片1片，其地址线13根，数据线8根，片选控制信号CS,无读写控制信号。SRAM： 8Kx8位芯片3片，地址线13根，数据线8根，片选控制线号CS,读写控制线号R/W； 2Kx8位芯片1片，地址 线11根，数据线8根，片选控制线号CS，读写控制线号R/W。(2) A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0CS0 8KCS1 8KCS2 8KCS3 8KCS41-2K CS0 = (A15*A14*A13) = Y0CS1 = (A15*A14*A13) = Y1CS2 = (A15*A14*A13)
11、= Y2CS3 = (A15*A14*A13) = Y3CS4 = (A15*A14*A13)*(A12*A11) =( (Y1 )*A12*A11) 数据总线：由于选择的存储芯片数据总线与CPU数据总线都是8位，因此不需要进行扩展，一一对应D7D0相联即 可。地址总线:系统程序区使用EPROM 8K容量，所以CPU的A12A0链接到EPROM的片内地址总线A12A0,CPU的A15A13地址线经过74LS138译码，输出Y0连接到EPROM的片选；用户程序区使用3片SRAM各8K容量，所以CPU的A12A0链接到SRAM的片内地址总线A12A0，CPU的 A15A13地址线经过74LS138
12、译码，输出Y1、Y2、Y3分别连接到3片SRAM的片选。系统工作区使用SRAM 2K容量，所以CPU的A10A0链接到SRAM的片内地址总线A10A0, CPU的A15A13 地址线经过74LS138译码，输出的Y7取反，与A12、A11相与，再取反连接到2K的SRAM片选。5. CPU performs a program; it accesses cache 3800 and accesses main memory 200. Known that Tc = 50ns, Tm = 250ns. Solving that the efficiency (e) and Ta of the ca
13、che/memory system.命中率 H = Ne / (NC + Nm) = 3800 / (3800 + 200) = 0.95主存慢于 cache 的倍率：r = tm / tc = 250ns / 50ns = 5访问效率：e = 1 / r + (1 r)H =1 / 5 + (1 5)X0.95 = 83.3%平均访问时间： ta = tc/ e =50ns / 0.833 = 60nsac6. We use 16M*8bit memory chip to form a 64M*16bit main memory module.Required that the capaci
14、ty of storage be expand, the access time be reduced.Questions:(1) How many 16M*8bit memory chips should be used?(2) Give the address length of each memory chip and address length of main memory module.(3) Descript select chip logic functions (片选逻辑函数) of each chip.Descript the connection way among en
15、coder, CPU and memory chips.(4) For an address (2345678)16, give its body number and address inside the body.(1)8个(2) 存储器芯片的地址长度为24 位。主存储器的地址长度为26 位(3) 每两片16M*8的芯片组成一组，每组构成一个16位的存储芯片，A2A25连接新的芯片 组的地址位。A0A1分别连接译码器，译码器连接CS0CS1CS2CS3。1234567右移两位是48D159，所以其体内地址为：48D159最低两位是11B,所以其体号为3。7. Known that efficiency of a cache/memory system is 0.85, Ta = 60ns, and cache is 4 times faster than memory. Solving that Tm and hit ratio of cache.因为：ta = tc / e 所以：tc = taXe = 60X0.85 = 510ns (cache 存取周期)tm = tcXr =510 X4 = 204ns (主存存取周期)因为：e= 1 / r + (1 - r )H
