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1、32位存储器（为简化，地址为5位）module Memorys(DataIn,WrEn,Adr,DataOut,clk,Run);input 31:0DataIn;input 4:0Adr;input WrEn,clk,Run;output 31:0DataOut;reg 31:0 DataOut;reg 31:0data31:0;integer count; always (posedge clk)beginif(WrEn=1b1 & Run=1b1)begindataAdr=DataIn;DataOut=DataOut;endif(Run=1b1)DataOut=dataAdr;if(Ru
2、n=1b0)for(count=0;count 32;count=count+1)datacount=8h00A62F02 * count;end、endmodule仿真图32位寄存器（为简化，地址为5位）module Registers(Ra,busA,Rb,busB,Rw,busW,clk,RegWr,Run);input 4:0 Ra,Rb,Rw;input clk,RegWr,Run;input 31:0busW;output 31:0 busA,busB;reg 31:0data31:0;integer count;assign busA=dataRa;assign busB=dataRb;always (posedge clk)beginif(RegWr=1b1 & Run=1b1)dataRw=busW;if(Run=1b0)beginfor(count=0;count 32;count=count+1)begindatacount=8h020CDA45 * count;endendendendmodule、仿真图
