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1、c Department of YiBin University designed by KingShine or WZHCYCLONE II系列FPGA存储器模块QCYCLONE II系列FPGA支持的双口 RAM 类型： 单端口 RAM 简单双端口 RAM 真双端口 RAM【在QUARTUS II中的库模块是AltSYNCRam】 混合真双端口 RAM【允许不同读写宽度】Q27 CYCLONE II系列FPGA存储器模块M4K寄存器清零的三种方法: 使用【异步】清零信号 aclr 上电复位器件assert the device-wide reset signal using the DEV
2、_CLRn option地址时钟使能应用于： 高速缓冲储存 地址使能默认为【低】电平 读地址时钟使能时：读地址锁存在使能时的地址上，读出的数据就是锁定的那个地址单元的数据。如：读地址锁存在0x05地址，则读出的数据就是0x05地址里面的数据值。 Figure 8 - shows an address clock enable block diagram. The address register output is fed back to its input via a multiplexer. The multiplexer output is selected by the address
3、 clock enable (addressstall) signal. Address latching is enabled when the addressstall signal goes high (active high). The output of the address register is then continuously fed into the input of the register until the addressstall signal goes low.address Dinclockrd addressao dress s ial Iq (synch)
4、地址内的数据如：1、2、3、4latched addressinside memory),0x05Figure 8-5. Cyclone II Address Clock Enable During Write Cycle Waveforminclock wraddress data wren addressstall latched address(inside memory)contents at aOcontents at a1XXX 01 X 02 XXX0405contents at a2 contents at a3 contents at a4 contents at a5CYC
5、LONE II系列FPGA的M4K存储器模块包括:写输入同步寄存器 流水线输出寄存器 这样的结构改善了系统性能 M4K 块布支持异步（*输入）寄存器 如果违反了存储器块地址寄存器建立、保持时间，可能导致存储器容量的改变。Q55 QUARTUS II 中的存储器模块类型： LPM_Ram_DP：参数化双端口 RAM LPM_Ram_DQ：输入输出端口分离的参数化RAM Alt_DpRam：参数化双端口 RAM Alt_QpRam：不支持 CYCLONE II 系列 Alt_SYNCRam:参数化真双端口 RAM单端口模式 不支持对同一地址同时读写 在写的同时读出数据输出，意思是在数据写入的期间输
6、出RAM中的数据，当输出寄存 器被避开的时候，新数据在同步时钟上升沿被写入。 不支持在读写寄存器上清零； 当读使能无效时，当前数据保持在输出端口； 在写期间，同步选择地址后，如果读使能有效，输出端口上的数据是 原来存在RAM中的数据。真双端口模式支持任意组合端口运行：两个读端口、两个写端口、一个读一个写分别不同时钟频率的 端口。Figure 8-9. Cyclone II Simple Dual-Port Timing Waveformswrclockwrenwrad dressan-1 卜:mn X 曲 X 日1 X 32 X 33a4(a5 X a6data (1)din-1 X斷 XXX
7、XXXXXXXXXXdin4 ”din 5乂 din.6rdclockrden读/写模式：两个时钟都有效rdaddressbnb0b1乂b3q(s yn ch)doutn-2 Xdoutn-1XdoutnXdoutOq (asynch)doutn-1XdoutnXdoutONote to Figure 8-9:(1) The crosses in the data waveform during read mean dont care. 写时钟控制：数据输入、写地址、写使能； 读时钟控制：数据输出、读地址、读使能； Cyclone II memory blocks can implement
8、read/write clock mode for simple dual-port memory. The write clock controls the blocks data inputs, write address, and write enable signals. The read clock controls the data output, read address, and read enable signals. The memory blocks support independent clock enables for each clock for the read
9、- and write-side registers. This mode does not support asynchronous clear signals for the registers. Figure 817 shows a memory block in read/write clock mode. Cyclone II存储块可以执行读/写时钟模式的简单双端口存储器。写时钟控制模块的数据 输入，写地址，写使能信号。读时钟控制数据输出，读地址，读使能信号。该储存块支 持独立的时钟使每个时钟的读，写方面的登记册。此模式支持对寄存器的异步清零信号。 Mixed-Port Read-D
10、uring-Write Mode This mode applies to a RAM in simple or true dual-port mode, which has one port reading and the other port writing to the same address location with the same clock.In this mode, you also have two output choices: old data or dont care. In Old Data Mode, a read-during-write operation
11、to different ports causes the RAM outputs to reflect the old data at that address location. In Dont Care Mode, the same operation results in a dont care or unknown valueon the RAM outputs.wren awren aNote to Figure 8-23:(1) Outputs arc not registered.wren bFigure 8-24. Cyclone Mixed-Port Read-During-Write: Doni Care Modeinclock address_a and address bwren bNote to Figure 8-24:(1) Outputs are not registered.
