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1、rjy4600_cnt60_160进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_cnt60_1 isport(clk:in std_logic; en:in std_logic; bcd10,bcd1:buffer std_logic_vector(3 downto 0); preset:in std_logic; co:out std_logic);end rjy4600_cnt60_1;architecture rtl of rjy4600_cnt60
2、_1 issignal co_1:std_logic; begin process(clk,preset) begin if preset=0 then bcd1=0000; else if clkevent and clk=1 then if en=1 then if bcd1=1001 then bcd1=0000; else bcd1=bcd1+1; end if; else if bcd1=0000 then bcd1=1001; else bcd1=bcd1-1; end if; end if; end if; end if; end process; process(clk,pre
3、set,bcd1) begin if preset=0 then bcd10=0000; co_1=0; else if clk=1 and clkevent then if en=1 then if bcd1=1000 and bcd10=0101 then co_1=1; elsif bcd1=1001 and bcd10=0101 then bcd10=0000; co_1=0; elsif bcd1=1001 then bcd10=bcd10+1; co_1=0; end if; else if bcd1=0001 and bcd10=0000 then co_1=0; elsif b
4、cd1=0000 and bcd10=0000 then bcd10=0101; co_1=1; elsif bcd1=0000 then bcd10=bcd10-1; co_1=0; else co_1=0; end if; end if; end if; end if; end process; co=not co_1; end rtl;rjy4600_cnt24：24进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_cnt24 isport(clk:in
5、 std_logic; en:in std_logic; bcd10,bcd1:buffer std_logic_vector(3 downto 0); end rjy4600_cnt24;architecture rtl of rjy4600_cnt24 isbegin process(clk) begin if clkevent and clk=1 then if en=1 then if bcd1=1001 then bcd1=0000; elsif bcd1=0011 and bcd10=0010 then bcd1=0000; else bcd1=bcd1+1; end if; el
6、se if bcd1=0000 and bcd10=0000 then bcd1=0011; elsif bcd1=0000 then bcd1=1001; else bcd1=bcd1-1; end if; end if; end if; end process; process(clk,bcd1) begin if clk=1 and clkevent then if en=1 then if bcd1=0011 and bcd10=0010 then bcd10=0000; elsif bcd1=1001 then bcd10=bcd10+1; end if; else if bcd1=
7、0000 and bcd10=0000 then bcd10=0010; elsif bcd1=0000 then bcd10=bcd10-1; end if; end if; end if; end process; end rtl; rjy4600_div1000：1000分频library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_div1000 isport(clk:in std_logic; q:out std_logic);end rjy4600_div1000;a
8、rchitecture rtl of rjy4600_div1000 issignal div:integer:=0; begin process(clk) begin if clkevent and clk=1 then if div=999 then div=0;q=1; else div=div+1;q=0; end if; end if; end process; end rtl; rjy4600_display：动态译码及显示扫描library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entit
9、y rjy4600_display isport(din0:in std_logic_vector(3 downto 0); din1:in std_logic_vector(3 downto 0); din2:in std_logic_vector(3 downto 0); din3:in std_logic_vector(3 downto 0); din4:in std_logic_vector(3 downto 0); din5:in std_logic_vector(3 downto 0); clk:in std_logic; led_sa:out std_logic; led_sb:
10、out std_logic; led_sc:out std_logic; led_a:out std_logic; led_b:out std_logic; led_c:out std_logic; led_d:out std_logic; led_e:out std_logic; led_f:out std_logic; led_g:out std_logic; led_dp:out std_logic);end rjy4600_display;architecture behave of rjy4600_display is signal seg:std_logic_vector(6 downto 0); signal sel:std_logic_vector(2 downto 0); signal num:std_logic_vector(3 downto 0); signal s:std_logic_vector(2 downto 0);begin led_sa=sel(0); led_sb=sel(1); led_sc=sel(2); led_a=seg(0); led_b=seg(1); led_c=seg(
