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1、附 录 英文文献4K X5043/X5045 512 x 8 BitCPU Supervisor with 4K SPI EEPROMDESCRIPTIONThese devices combine four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces boar
2、d space requirements, and increases reliability.Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code.The Watchdog Timer provides an independen
3、t protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling t
4、he power.The devices low VCC detection circuitry protects the users system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds ar
5、e available, however, Xicors unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.The memory portion of the device is a CMOS Serial EEPROM array with Xicors block lock protection. The array is int
6、ernally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.The device utilizes Xicors proprietary Direct Writecell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.FE
7、ATURES Selectable time out watchdog timer Low VCCdetection and reset assertionFive standard reset threshold voltagesRe-program low VCCreset threshold voltageusing special programming sequence.Reset signal valid to VCC= 1V Long battery life with low power consumption50A max standby current, watchdog
8、on10A max standby current, watchdog off2mA max active current during read 2.7V to 5.5V and 4.5V to 5.5V power supplyversions 4Kbits of EEPROM1M write cycle endurance Save critical data with Block LockmemoryProtect 1/4, 1/2, all or none of EEPROM array Built-in inadvertent write protectionWrite enabl
9、e latchWrite protect pin 3.3MHz clock rate Minimize programming time16-byte page write modeSelf-timed write cycle5ms write cycle time (typical) SPI modes (0,0 & 1,1) Available packages8-lead MSOP, 8-lead SOIC, 8-pin PDIP14-lead TSSOPPIN DESCRIPTIONSSerial Output (SO)SO is a push/pull serial data out
10、put pin. During a readcycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.Serial Input (SI)SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of t
11、he serial clock.Serial Clock (SCK)The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input.Chip Select (CS)
12、When CS is high, the X5043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043/45 will be in the standby power mode. CS low enables the X5043/45, placing it in the active power mode. It should be noted that after power-up, a high
13、 to low transition on CS is required prior to the start of any operation.Write Protect (WP)When WP is low, nonvolatile writes to the X5043/45 are disabled, but the part otherwise functions normally.When WP is held high, all functions, including non volatile writes operate normally. WP going low whil
14、e CS is still low will interrupt a write to the X5043/45. If the internal write cycle has already been initiated, WP going low will have no affect on a write.Reset (RESET, RESET)X5043/45, RESET/RESET is an active low/HIGH,open drain output which goes active whenever VCC falls below the minimum VCCse
15、nse level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of CS will reset the watchdog timer.PRINCIPLES OF OPE
16、RATIONPower On ResetApplication of power to the X5043/X5045 activates a Power On Reset Circuit. This circuit pulls the RESET/RESET pin active. RESET/RESET prevents the system microprocessor from starting to operate with insuf-ficient voltage or prior to stabilization of the oscillator.When VCC exceeds the device V
