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1、 Abstract - With the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space
2、environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAE) CMOS Ultra Low Power Radiation Tolerant (CULP
3、RiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices. Index Terms Single Event Effects, Hardened-By-Design, microcontroller, radiation effects. I. INTRODUCTION NASA constantly strives to provide the best capture of science while operating in a space radiation en
4、vironment using a minimum of resources 1,2. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercial state-of-the-art technologies, NASAs performance of this task is quite challenging. One method of alle
5、viating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD). Building custom-type HBD devices using design libraries and automated design tools may provide James W. Howard Jr. is with Jacks
6、on & Tull Chartered Engineers, c/o NASA/GSFC, Code 561.4, Greenbelt, MD 20771 (USA), phone: 301-286-1023, fax: 301-286-4699, email: jim.howardgsfc.nasa.gov Kenneth A. LaBel is with NASA/GSFC, Code 561.4, Greenbelt, MD 20771 USA), phone: 301-286-9936, email: Kenneth.A.Labelnasa.gov Martin A. Carts is
7、 with Muiz Engineering Inc., c/o NASA/GSFC, Code 561.4, Greenbelt, MD 20771 (USA), phone: 301-286-2600, email: mcartspop500.gsfc.nasa.gov Christina Seidleck is with Muiz Engineering Inc., c/o NASA/GSFC, Code 561.4, Greenbelt, MD 20771 (USA), phone: 301-286-1009, email: cseidlecpop700.gsfc.nasa.gov J
8、ody W. Gambles is with the University of Idaho, Center for Advanced Microelectronics & Biomolecular Research, Post Falls, ID 83854 (USA), phone: 208-262-2012, email: jgamblescambr.uidaho.edu Steven L. Ruggles is with NASA/LaRC Mailstop 152D, Hampton, VA 23681 (USA), phone: 757-864-1515, email: Steve
9、n.L.Rugglesnasa.gov NASA the solution it needs to meet stringent science performance specifications in a timely, cost-effective, and reliable manner. However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed; what types o
10、f tests are required for HBD validation? II. TESTING HBD DEVICES CONSIDERATIONS Test methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD-883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required
11、for device validation. So what is unique to HBD devices? As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the
12、device hardness. That is, by using test chips, can we “qualify” a future device using the same library? Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by
13、 designing a new device using Vendor As library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked. How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA
14、design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived. Other considerations includ
15、e speed of operation and operating voltage. For example, if the test chip was Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerJames W. Howard Jr., Senior Member, IEEE, Kenneth A. LaBel, Member, IEEE, Martin A. Carts, Member, IEEE, Christina Seidleck,
16、 Jody W. Gambles, Senior Member, IEEE, and Steven L. Ruggles tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., non-static operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies. The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application mus
