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1、Lecture 32 Improved Open-Loop Comparators and Latches(6/26/14)Page 32-1 CMOS Analog Circuit Design P.E.Allen-2016 LECTURE 32 IMPROVED OPEN-LOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple Latches Summary CMOS Analog Circuit Design,3rd Edition Reference Pages 46
2、9-488 Lecture 32 Improved Open-Loop Comparators and Latches(6/26/14)Page 32-2 CMOS Analog Circuit Design P.E.Allen-2016 AUTOZEROING Principle of Autozeroing Use the comparator as an op amp to sample the dc input offset voltage and cancel the offset during operation.Comments:The comparator must be st
3、able in the unity-gain mode(self-compensating comparators are ideal,the two-stage comparator would require compensation to be switched in during the autozero cycle.)Complete offset cancellation is limited by charge injection Lecture 32 Improved Open-Loop Comparators and Latches(6/26/14)Page 32-3 CMO
4、S Analog Circuit Design P.E.Allen-2016 Differential Implementation of Autozeroed Comparators Lecture 32 Improved Open-Loop Comparators and Latches(6/26/14)Page 32-4 CMOS Analog Circuit Design P.E.Allen-2016 Single-Ended Autozeroed Comparators Noninverting:Inverting:Comment on autozeroing:Need to be
5、careful about noise that gets sampled onto the autozeroing capacitor and is present on the comparison phase of the process.Lecture 32 Improved Open-Loop Comparators and Latches(6/26/14)Page 32-5 CMOS Analog Circuit Design P.E.Allen-2016 HYSTERESIS Influence of Input Noise on the Comparator Comparato
6、r without hysteresis:Comparator with hysteresis:Voltage Regulator with input voltage having too large of source resistance,RS:vinvoutVOHVOLttVTRP+VTRP-Fig.8.4-6BvinvoutVOHVOLComparatorthresholdttFig.8.4-6AEnableVONVoltageRegulatorCLRLRS+-VIN+-150604-01Lecture 32 Improved Open-Loop Comparators and La
7、tches(6/26/14)Page 32-6 CMOS Analog Circuit Design P.E.Allen-2016 Use of Hysteresis for Comparators in a Noisy Environment Transfer curve of a comparator with hysteresis:Hysteresis is achieved by the use of positive feedback Externally Internally vOUTvINVTRP+VTRP-VOHVOLFig.8.4-5vOUTvINVOHVOL00R1R2(V
8、OH-VOL)VTRP+VTRP-Counterclockwise BistableClockwise BistableLecture 32 Improved Open-Loop Comparators and Latches(6/26/14)Page 32-7 CMOS Analog Circuit Design P.E.Allen-2016 Noninverting Comparator using External Positive Feedback Circuit:Upper Trip Point:Assume that vOUT=VOL,the upper trip point oc
9、curs when,0=R1R1+R2VOL +R2R1+R2VTRP+VTRP+=-R1R2 VOL Lower Trip Point:Assume that vOUT=VOH,the lower trip point occurs when,0=R1R1+R2VOH +R2R1+R2VTRP-VTRP-=-R1R2 VOH Width of the bistable characteristic:Vin=VTRP+-VTRP-=R1R2 VOH-VOL Lecture 32 Improved Open-Loop Comparators and Latches(6/26/14)Page 32
10、-8 CMOS Analog Circuit Design P.E.Allen-2016 Inverting Comparator using External Positive Feedback Circuit:Upper Trip Point:vIN=VTRP+=R1R1+R2VOH Lower Trip Point:vIN=VTRP-=R1R1+R2VOL Width of the bistable characteristic:Vin=VTRP+-VTRP-=R1R1+R2 VOH-VOL Lecture 32 Improved Open-Loop Comparators and La
11、tches(6/26/14)Page 32-9 CMOS Analog Circuit Design P.E.Allen-2016 Horizontal Shifting of the CCW Bistable Characteristic Circuit:Upper Trip Point:VREF =R1R1+R2VOL +R2R1+R2VTRP+VTRP+=R1+R2R2VREF-R1R2 VOL Lower Trip Point:VREF =R1R1+R2VOH +R2R1+R2VTRP-VTRP-=R1+R2R2VREF-R1R2 VOH Shifting Factor:R1+R2 R
12、2 VREF Lecture 32 Improved Open-Loop Comparators and Latches(6/26/14)Page 32-10 CMOS Analog Circuit Design P.E.Allen-2016 Horizontal Shifting of the CW Bistable Characteristic Circuit:Upper Trip Point:vIN=VTRP+=R1R1+R2VOH +R2R1+R2VREF Lower Trip Point:vIN=VTRP-=R1R1+R2VOL +R2R1+R2VREF Shifting Facto
13、r:R2R1+R2 VREF Lecture 32 Improved Open-Loop Comparators and Latches(6/26/14)Page 32-11 CMOS Analog Circuit Design P.E.Allen-2016 Example 32-1 Design of an Inverting Comparator with Hysteresis Use the inverting bistable to design a high-gain,open-loop comparator having an upper trip point of 1V and
14、a lower trip point of 0V if VOH=2V and VOL=-2V.Solution Putting the values of this example into the above relationships gives 1=R1R1+R2 2+R2R1+R2VREF and 0=R1R1+R2(-2)+R2R1+R2VREF Solving these two equations gives 3R1=R2 and VREF=(2/3)V.Lecture 32 Improved Open-Loop Comparators and Latches(6/26/14)P
15、age 32-12 CMOS Analog Circuit Design P.E.Allen-2016 Hysteresis using Internal Positive Feedback Simple comparator with internal positive feedback:VSSIBiasvo1vo2vi1vi2M1M2M3M4M6M7M5M8VDDFig.8.4-11Lecture 32 Improved Open-Loop Comparators and Latches(6/26/14)Page 32-13 CMOS Analog Circuit Design P.E.A
16、llen-2016 Internal Positive Feedback-Upper Trip Point Assume that the gate of M1 is on ground and the input to M2 is much smaller than zero.The resulting circuit is:M1 on,M2 off M3 on,M6 on(active),M4 and M7 off.vo2 is high.M6 wants to source the current i6=W6/L6W3/L3 i1 As vin begins to increase towards the trip point,the current flow through M2 increases.When i2=i6,the upper trip point will occur.I5=i1+i2=i3+i6=i3+W6/L6W3/L3i3=i3 1+W6/L6W3/L3 i1=i3=I51+(W6/L6)/(W3/L3)Also,i2=I5-i1=I5-i3 Knowin
