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1、本文格式为Word版，下载可任意编辑FPGA常见的错误 FPGA常见的错误 Quartus II常见错误 1.Found clock-sensitive change during active clock edge at time Timing analysis settings.Individual clocks. 6.Timing characteristics of device EPM570T144C5 are preliminary 理由:由于MAXII 是比較新的元件在 QuartusII 中的時序并不是正式版的,要等 Service Pack 措施:只影响 Quartus 的
2、Waveform 7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled 措施:将setting中的timing Requirements&Option-More Timing Setting-setting-Enable Clock Latency中的on改成OFF 8.Found clock high time violation at 14.8 ns on register 理由:违反了steup/hold时间，理应是后
3、仿真，看看波形设置是否和时钟沿符合steup/hold时间 措施:在中间加个寄放器可能可以解决问题 9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay 理由:时钟抖动大于数据延时,当时钟很快，而if等类的层次过多就会展现这种问题,但这个问题多是在器件的最高频率中才会展现 措施：setting-timing Requirements&Options-Default required fma
4、x 改小一些，如改到50MHZ 10.Design contains are preliminary 理由：目前版本的QuartusII只对该器件供给初步的时序特征分析 措施：假设坚持用目前的器件，无须打理该警告。关于进一步的时序特征分析会在后续版本的Quartus得到完善。 20.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family 理由：用analyze_latches_as_synchronous_e
5、lements setting可以让Quaruts II来分析同步锁存，但目前的器件不支持这个特性 措施：无须打理。时序分析可能将锁存器分析成回路。但并不确定分析正确。其后果可能会导致显示指点用户：变更设计来消释锁 存器 21.Warning:Found xx output pins without output pin load capacitance assignment（网友：gucheng82供给） 理由：没有给输出管教指定负载电容 措施：该功能用于估算TCO和功耗，可以不打理，也可以在Assignment Editor中为相应的输出管脚指定负载电容，以消释警告 22.Warning:
6、 Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew 理由：使用了行波时钟或门控时钟，把触发器的输出当时钟用就会报行波时钟，将组合规律的输出当时钟用就会报门控时钟 措施：不要把触发器的输出当时钟，不要将组合规律的输出当时钟，假设本身如此设计，那么无须打理该警告 23.Warning (10268): Verilog HDL information at lcd7106.v(6
7、3): Always Construct contains both blocking and non-blocking assignments 理由： 一个always模块中同时有阻塞和非阻塞的赋值 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list -没把singal放到process（）中 2 Warning: Found pins ing as undefined clocks and/or memory enablesInfo: Assuming node CLK is an undefined clock 3
