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1、1Chapter 9 Counters計數器計數器1.Asynchronous Counter Operation 非同步式計數器的運作非同步式計數器的運作2.Synchronous Counter Operation 同步式計數器的運作同步式計數器的運作3.Up/Down Synchronous Counters 上上 / / 下數的同步式計數器下數的同步式計數器4.Design of Synchronous Counters 同步式計數器的設計同步式計數器的設計5.Cascaded Counters 串接計數器串接計數器6.Counter Decoding 計數器的解碼計數器的解碼7.Co
2、unter Applications 計數器的應用計數器的應用8.Troubleshooting 檢修檢修9.Logical Symbols with Dependency Notation 具有相依註標的邏輯符號具有相依註標的邏輯符號10.Programmable Logic 可程式邏輯可程式邏輯Digital System Application 數位系統的應用數位系統的應用2Figure 8-40 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.Thomas L. FloydDig
3、ital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.Flip-Flop Applications 正反器的用途正反器的用途除法器除法器JKClkQQ00Q0Q0不變0101Reset1010Set11Q0Q0轉態3Figure 9-1 A 2-bit asynchronous binary counter. Thomas L. FloydDigital Fundamentals, 8eCopyright 2003
4、 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計數器的運作非同步式計數器的運作Figure 9-2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green.100111004Figure 9-3 Three-bit asynchronous binary counter and its timing dia
5、gram for one cycle. Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計數器的運作非同步式計數器的運作5Figure 9-4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.Thomas L. FloydDigital Fundamental
6、s, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計數器的運作非同步式計數器的運作6Figure 9-5 Four-bit asynchronous binary counter and its timing diagram. Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, Ne
7、w Jersey 07458All rights reserved.1. 非同步式計數器的運作非同步式計數器的運作例題9-1 如圖9-5所示為一個4位元的非同步二進制計數器, 每一個正反器都是負緣觸發而且有一個10ns的極際延遲時間. (1)設 計各正反器輸出的時序圖, (2)算出從Clock輸入加訊號進去到Q3輸出的延遲時間, (3)算出 最 高 工 作 頻 率.Sol:(2) tp(Total) = 4 x 10ns = 40ns(3) fmax = 1/ tp(Total) = 1/40ns = 25MHz7Thomas L. FloydDigital Fundamentals, 8eC
8、opyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計數器的運作非同步式計數器的運作Figure 9-6 An asynchronously clocked decade counter with asynchronous recycling.8Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River,
9、New Jersey 07458All rights reserved.例題例題9-2 證明一個非同步的計數器如證明一個非同步的計數器如何除何除12, 從二進制的從二進制的0000算到算到1011.1. 非同步式計數器的運作非同步式計數器的運作Figure 9-7 Asynchronously clocked modulus-12 counter with asynchronous recycling.很尖很尖銳的銳的脈波脈波9FigureA-21 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers
10、 are in parentheses, and all J and K inputs are internally connected HIGH.)Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計數器的運作非同步式計數器的運作10Figure A-22 Two configurations of the 74LS93A asynchronous count
11、er. (The qualifying label, CTR DIV n, indicates a counter with n states.)Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計數器的運作非同步式計數器的運作11Figure A-23 74LS93A connected as a modulus-12 counter.Thomas L. Fl
12、oydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計數器的運作非同步式計數器的運作例題例題9-3 證明證明74LS93A 如何作為如何作為一個除一個除12的計數器的計數器.12A 2-bit synchronous binary counter.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Educat
13、ion, Inc.Upper Saddle River, New Jersey 07458All rights reserved.2. 同步式計數器的運作同步式計數器的運作Figure 9-10 Timing diagram for the counter of Figure 9-11.13Figure 9-9 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).Thomas L. FloydD
14、igital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.2. 同步式計數器的運作同步式計數器的運作第一個脈波第一個脈波第二個脈波第二個脈波第三個脈波第三個脈波第四個脈波第四個脈波解釋前一頁每次解釋前一頁每次Clock來時來時Q0及及Q1的變化的變化14Figure 9-11 A 3-bit synchronous binary counter. Thomas L. FloydDigital Fundamental
15、s, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.2. 同步式計數器的運作同步式計數器的運作Figure 9-12 Timing diagram for the counter of Figure 9-14.15Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458A
16、ll rights reserved.2. 同步式計數器的運作同步式計數器的運作FF2在在Q0Q1同同時為時為1時時,下一下一個脈波來會改個脈波來會改變狀態變狀態, FF3則則在在Q0Q1Q2同時同時為為1時時,下一個下一個脈波來才會改脈波來才會改變狀態變狀態, Figure 9-13 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.16Figure 9-14 A synchronous BCD decade counter.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.2. 同步式計數器的運作同步式計數器的運作Figure 9-15 Timing d
