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1、Chapter 7P7.1. Assume that all nodes start at 0V. The first row outputs will be at . Since these nodes are also the gate nodes of the second row of transistors, their source nodes will be at . Likewise, the last row of transistors have voltages of . However, this value is below 0V so we leave them a
2、t 0V.P7.2. (a)ABOut00Z01110Z 11Z(b)ABOut001011100111 (c)ABCOut000Z001Z010001111000101Z1100111Z (d)ABCOut00000010010001111000101011001111P7.3. (a) First calculate VQ. Since this is slightly below 1.3V (voltage at which the PMOS turns on), we assume that the PMOS is slightly on. Since the PMOSs VGS is
3、 quite low (because Q is high) and its VDS is quite high (because is low), the transistor is very likely in saturation. Similarly for the NMOS, because its VGS is high and its VDS is low, its likely in the linear region. Equating the two currents:For simplicity we shall assume that and .Solve to pro
4、duce:When the CLK goes low, the intermediate output suffers from clock feedthough. To calculate the effects of clock feedthrough, let us first compute the capacitances involved. The capacitance from the clock signal to Q is:The capacitance from the Q to ground is:The capacitive feedthrough equation
5、is:To get the new value of , first determine the determine the regions of operation of the transistors in the inverter by calculating VS. Then, once again, use the current equations to determine.Since the new voltage of VQ is still greater than the switching voltage, the transistors are in the same
6、regions:(b) In this case and . Clock feedthrough has no effect since the transmission gate CLK signals cancel each other out.P7.4.a.ABCOut00000010010001111001101111011111b.ABCOut00010010010101111001101011011111c.ABCOut00010010010101111000101011001110d.ABCOut00000010010101111001101111011111P7.5.a.b.P
7、7.6.a.b.c.d.P7.7. Assuming that one of the transistors in each transmission gate is being driven by a min-sized inverter:a.b.P7.8.a.b.c.d.e.P7.9. In both of these cases, the logical effort is the same due to the fact that the longest path from output to ground is three transistors long. Assume that
8、the CLK arrives ahead of the signals. Then, P7.10. We will use 0.18um technology and the node names below: For the two inverter inputs:For the pass gate inputs:At node x:At node y:At node Out:The shortest path is through the one of the GND input nodes to the output:The longest path is through one of
9、 the inverters to the output.P7.11. At : .When the a goes high the first time, the voltage at X would be computed using the charge-sharing formula:But because the maximum allowable voltage at node x is 0.734V, set Then recomputed VF:When Phi goes down, and VX and VY remains the same.The next time th
10、e Phi goes up, all the internal nodes are 0.When Phi goes down, and VX and VY remains at 0.P7.12.StaticDynamicSpeedIncrease in temperature results in reduced speed to due to decrease in on-current.Increase in temperature results in reduced speed to due to decrease in on-current.PowerIncrease in temp
11、erature results in increased power due to increase in short-circuit current as a result of reduced speed.Increase in temperature results in increased power due to increase in short-circuit current as a result of reduced speed.LeakageDoes not affect operation much, but increases static power.Increase
12、 in temperature results in increase of leakage current and possible loss of value.P7.13.a. The input settings that give you the worst-case charge sharing are any of and both of . Essentially, what you are doing it trying to create the greatest amount of parasitic capacitances without creating a path
13、 to GND.b. Assuming that transistors share nodes to reduce capacitance.The actual voltage would be larger than this since the internal node cannot rise above VDD-VT.c. This circuit fails if the worse case voltage falls below the switching voltage which can be computed to be VS=0.92V. Therefore, the
14、circuit will operate properly.P7.14. Both of these circuits act as latches. When EN is on, there is a path from the output to either VDD or GND. The first latch is better than the second because the second latch suffers from charge sharing. When EN is off, there is no path from the output to either o
