OPA177Precision OPERATIONAL AMPLIFIER

OPA177Precision OPERATIONAL AMPLIFIER OPA177Precision OPERATIONAL AMPLIFIER SBOS008 1990 Burr-Brown CorporationPDS-1081EPrinted in U.S.A. August, 1997 OPA177Precision OPERATIONAL AMPLIFIER OPA177 SPECIFICATIONS At VS = 15V, TA = +25C, unless otherwise noted. OPA177F PARAMETER OFFSET VOLTAGEInput Offset Voltage Long-Term Input Offset(1) Voltage Stability Offset Adjustment Range Power Supply Rejection RatioINPUT BIAS CURRENTInput Offset CurrentInput Bias CurrentNOISE Input Noise VoltageInput Noise CurrentINPUT IMPEDANCEInput Resistance INPUT VOLTAGE RANGECommon-Mode Input Range(4)Common-Mode RejectionOPEN-LOOP GAIN Large Signal Voltage GainOUTPUT Output Voltage Swing 1Hz to 100Hz(2)1Hz to 100HzDifferential Mode(3)Common-Mode 26 CONDITION MIN TYP100.3 RP = 20k VS = 3V to 18V 31250.30.5854.5452021414012,000141312.5600.30.6403.51.3 604.521.52150MAX25 MIN OPA177GTYP200.4T120TTTT 18.5 TTTT6000TTTTTTTTT TTT2.82.8TMAX60 UNITSVV/MomVdBnAnAnVrmspArmsM G VdBV/mVVVV V/sMHzmWmWmA 115110 VCM = 13VRL ≥ 2k VO = 10V(5)RL ≥ 10k RL ≥ 2k RL ≥ 1k 13130511013.512.512 T1152000TTT Open-Loop Output ResistanceFREQUENCY RESPONSESlew Rate Closed-Loop BandwidthPOWER SUPPLYPower ConsumptionSupply Current RL ≥ 2k G = +1VS = 15V,NoLoadVS = 3V, No LoadVS = 15V,NoLoad 0.10.4 TT At VS = 15V, –40C ≤ TA ≤ +85C, unless otherwise noted.OFFSET VOLTAGEInput Offset VoltageAverage Input Offset Voltage Drift Power Supply Rejection RatioINPUT BIAS CURRENTInput Offset Current Average Input Offset Current Drift(6) Input Bias Current Average Input Bias Current Drift(6) INPUT VOLTAGE RANGECommon-Mode Input RangeCommon-Mode RejectionOPEN-LOOP GAIN Large Signal Voltage GainOUTPUT Output Voltage SwingPOWER SUPPLYPower ConsumptionSupply Current T Same as specification for product to left. NOTES: (1) Long-Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs time over extended periods after the first 30 days of operation. Excludingthe initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2V. (2) Sample tested. (3) Guaranteed by design. (4) Guaranteedby CMRR test condition. (5) To insure high open-loop gain throughout the 10V output range, AOL is tested at –10V ≤ VO ≤ 0V, 0V ≤ VO ≤ +10V, and –10V ≤ VO ≤ +10V.(6) Guaranteed by end-point limits. 13120210012 150.1 VS = 3V to 18V 110 1200.51.50.58 2.240440400.3 106 200.7115TTT15 4.5856601001.2 VV/CdBnApA/CnApA/C VCM = 13VRL≥2k , VO=10V RL ≥ 2k VS=15V,NoLoadVS=15V,NoLoad 13.5140600013602 7525 T1101000T TT4000TTT TT VdBV/mVVmWmA OPA177 2 OPA177Precision OPERATIONAL AMPLIFIER PIN CONFIGURATION Top View DIP/SOIC ABSOLUTE MAXIMUM RATINGS Power Supply Voltage.......................................................................22VDifferential Input Voltage...................................................................30VInput Voltage.......................................................................................VSOutput Short Circuit.................................................................ContinuousOperating Temperature: Plastic DIP (P), SO-8 (S)..............................................–40C to +85CθJA (PDIP).................................................................................100C/WθJA (SOIC).................................................................................160C/WStorage Temperature: Plastic DIP (P), SO-8 (S)............................................–65C to +125CJunction Temperature....................................................................+150CLead Temperature(soldering, 10s) P packages...........................+300C (soldering, 3s) S package...............................+260C Offset Trim –In+InV– 1234 8765 Offset TrimV+VO No Internal Connection PACKAGE/ORDERING INFORMATION PACKAGEDRAWINGNUMBER(1) 006006182 TEMPERATURE RANGE–40C to +85C–40C to +85C–40C to +85C PRODUCTOPA177FPOPA177GPOPA177GS PACKAGE8-Pin Plastic DIP8-Pin Plastic DIPSO-8 Surface-Mount Any integrated circuit can be damaged by ESD. Burr-Brownrecommends that all integrated circuits be handled withappropriate precautions. ESD can cause damage rangingfrom subtle performance degradation to complete devicefailure. Precision integrated circuits may be more suscep-tible to damage because very small parametric changescould cause the device not to meet published specifications.Burr-Brown’s standard ESD test method consists of five1000V positive and negative discharges (100pF in serieswith 1.5k ) applied to each pin. Failure to observe proper handling procedures could resultin small changes to the OPA177’s input bias current. NOTE: (1) For deta。