第第2章章 EDA设计流程及其工具设计流程及其工具 课程讲义课程讲义合肥工业大学 彭良清 本章内容1.EDA设计的一般步骤2.常用EDA工具软件3.使用MAX+PLUS II软件设计过程4.使用Quartus II软件设计过程5.硬件设计和软件设计的时间协调6.设计的几个问题 EDA设计的一般步骤1.电路的模块划分2.设计输入3.器件和引脚指配4.编译与排错5.功能仿真和时序仿真6.编程与配置，设计代码的芯片运行 电路的模块划分v人工人工 根据电路功能 进行 模块划分模块划分v合理的模块划分 关系到1.电路的性能2.实现的难易程度v根据模块划分和系统功能 确定确定： PLD芯片型号芯片型号模块划分后，就可以进行模块划分后，就可以进行 具体设计具体设计 了了 设计输入一般EDA软件允许3种设计输入：1.HDL语言2.电路图3.波形输入 何为 ？ 器件和引脚指配v器件指配F为设计输入 选择合适的PLD器件型号v何谓引脚指配F将设计代码（图形）中的端口（端口（PORT）） 和 PLD芯片的引脚芯片的引脚 （（PIN）） 对应起来的.v指配文件FMAX+PLUS II： “ *.acf ” FQuartus II： “ *.qsf ” 器件和引脚指配的方法方法有2种1.在软件的菜单界面中指配2.修改指配文件（是文本文件） 菜单界面中指配 修改指配文件vCHIP io_2d_lockvBEGINv|iVD :INPUT_PIN = 7;v|iHD :INPUT_PIN = 8;v|iDENA :INPUT_PIN = 6;v|iCLK : INPUT_PIN = 211;v|oCLK : OUTPUT_PIN = 237;v|oVD :OUTPUT_PIN = 234;v|oHD : OUTPUT_PIN = 233;v|oDENA :OUTPUT_PIN = 235;v.................................................vDEVICE = EPF10K30AQC240-2;vEND;v........................................ 编译与排错编译过程有2种，作用分别为：1.语法编译：只是综合并输出网表F编译设计文件，综合产生门级代码F编译器只运行到综合这步就停止了F编译器只产生估算的延时数值2.完全的编译：包括编译，网表输出，综合，配置器件F编译器除了完成以上的步骤，还要将设计配置到ALTERA的器件中去F编译器根据器件特性产生真正的延时时间和给器件的配置文件 功能仿真和时序仿真v仿真的概念：在设计代码下载到芯片前，在EDA软件中对设计的输出进行波形仿真。
v常用的2种仿真模式1.功能仿真对设计的逻辑功能进行仿真2.时序仿真对设计的逻辑功能和信号的时间延时进行仿真v仿真前还要做的工作输入信号的建立Quartus II软件中软件中关于仿真的原文关于仿真的原文 2种 仿真文件1.矢量波形文件： v a Vector Waveform File (.vwf)2.文本矢量文件v a text-based Vector File (.vec), 编程与配置最后，最后， 如果仿真如果仿真 也正确也正确 的话，的话， 那我们就可以那我们就可以 将设计代码将设计代码 配置或者编程配置或者编程 到到 芯片芯片 中了中了v编程的文件类型对于CPLD或者EPC2，，ECS1等配置芯片，编程文件扩展名为：“ *.POF “v配置的文件类型对于FPGA芯片，配置文件扩展名为：“ *.SOF “ 硬件设计和软件设计的时间协调1.软件模块划分，器件的初步信号确定（主要是根据需要的I/O引脚的数量）2.软件设计，硬件外围电路设计和器件选择 3.软件仿真4.仿真完成后，器件信号的重新审核，进行硬件电路图设计5.综合调试6.完成 设计的几个问题v如何组织多个设计文件的系统？，项目的概念。
v时钟系统如何设计？v电路的设计功耗v高速信号的软件和硬件设计 The end. 以下内容以下内容为为正文的引用，正文的引用，可不阅读可不阅读 常用EDA工具软件vEDA软件方面，大体可以分为两类：1.PLD器件厂商提供的EDA工具较著名的如：I.Altera公司的 Max+plus II和Quartus II、II.Xilinx公司的Foundation Series、III.Latice-Vantis公司的ispEXERT System2.第三方专业软件公司提供的EDA工具常用的有：I.Synopsys公司的FPGA Compiler II、II.Exemplar Logic公司的LeonardoSpectrum、III.Synplicity公司的Synplifyv第三方工具软件是对CPLD/FPGA生产厂家开发软件的补充和优化，如通常认为Max+plus II和Quartus II对VHDL/Verilog HDL逻辑综合能力不强，如果采用专用的HDL工具进行逻辑综合，会有效地提高综合质量 ALTERA 公司的公司的EDA合作伙伴合作伙伴 硬件描述语言：起源v是电子电路的文本描述。
v最早的发明者：美国国防部，美国国防部，VHDL,1983v大浪淘沙，为大者二：VHDL 和 Verilog HDLv其他的小兄弟：ABEL、、AHDL、、System Verilog、、System C 一个D触发器的VHDL代码例子1.-- VHDL code position: p83_ex4_11_DFF12.-------------------------------------------------------------------------------3.-- LIBARY IEEE;4.-- USE IEEE.STD_LOGIC_1164.ALL;5.ENTITY DFF1 IS 6.PORT (CLK:INBIT;7.D:INBIT;8.Q:OUTBIT9.);10.END ENTITY DFF1;11.ARCHITECTURE bhv OF DFF1 IS12.BEGIN13.PROCESS(CLK)14.BEGIN15.IF CLK'EVENT AND (CLK='1') AND ( CLK'LAST_VALUE = '0') THEN16.-- 严格的CLK信号上升沿定义17.Q <= D;18.END IF;19.END PROCESS;20.END ARCHITECTURE bhv;代码实体（5－10）代码结构体（11－20） 如何使用VHDL来设计电路？vVHDL设计电路的的5步曲1.语言编码2.逻辑综合3.功能和时序仿真4.器件适配5.器件编程 使用MAX+PLUS II软件的设计过程 MAX+PLUS II设计过程说明1.Compiler Netlist Extractor（编译器网表提取器）（编译器网表提取器）:通过该过程生成设计项目的网表文件,2.Database Builder(数据库构建器 ):用于将所有的设计文件集成到项目数据库中 如果指定端口的实体已被抽取. 则从盘中读取. cnf文件信息就可以了, 因而节省了时间. 3.Logic Synthesizer (逻辑综合器):选择合适的逻辑化简算法,去除冗余和无用逻辑,有效使用器件的逻辑资源. 4.Fitter(适配器)将电路适配到某个PLD器件中。
5.Timing SNF Extractor(时序SNF文件提取器)产生用于时序仿真的网表文件6.Assembler（汇编器）产生用于器件编程的目标代码 其他的HDL综合工具vAltera公司1.MAX+PLUS II 10.2（已经停止发行，新器件不支持）2.QUARTUS II 5.0（推荐使用）vXilinx 公司1.ISE 7.0：Xilinx公司集成开发的工具 2.Foundation: Xilinx公司早期开发工具，逐步被ISE取代 3.ISE Webpack： Webpack是xilinx提供的免费开发软件，功能比ISE少一些，可以从xilinx网站下载 有了HDL语言后？硬件设计人员硬件设计人员 的工作过程 已经 类似与 软件设计人员软件设计人员，那么这种模式的好处是？让我们先看看原来是如何做的－> Compiler Netlist Extractor（编译器网表提取器）（编译器网表提取器）vThe Compiler module that converts each design file in a project (or each cell of an EDIF Input File) into a separate binary CNF. The filename(s) of the CNF(s) are based on the project name. ExamplevThe Compiler Netlist Extractor also creates a single HIF that documents the hierarchical connections between design files.vThis module contains a built-in EDIF Netlist Reader, Verilog Netlist Reader, VHDL Netlist Reader, and converters that translate ADFs and SMFs for use with MAX+PLUS II. vDuring netlist extraction, this module checks each design file for problems such as duplicate node names, missing inputs and outputs, and outputs that are tied together.v返回 Database Builder(数据库构建器 ):vThe Compiler module that builds a single, fully flattened project database that integrates all the design files in a project hierarchy. vThe Database Builder uses the HIF to link the CNFs that describe the project. Based on the HIF data, the Database Builder copies each CNF into the project database. Each CNF is inserted into the database as many times as it is used within the original hierarchical project. The database thus preserves the electrical connectivity of the project.vThe Compiler uses this database for the remainder of project processing. Each subsequent Compiler module updates the database until it contains the fully optimized project. In the beginning, the database contains only the original netlists; at the end, it contains a fully minimized, fitted project, which the Assembler uses to create one or more files for device programming. vAs it creates the database, the Database Builder examines the logical completeness and consistency of the project, and checks for boundary connectivity and syntactical errors (e.g., a node without a source or destination). Most errors are detected and can be easily corrected at this stage of project processing.v返回 Logic SynthesizervThe Compiler module that synthesizes the logic in a project's design files. vUsing the database created by the Database Builder, the Logic Synthesizer calculates Boolean equations for each input to a primitive and minimizes the logic according to your specifications. vFor projects that use JK or SR flipflops, the Logic Synthesizer checks each case to determine whether a D or T flipflop will implement the project more efficiently. D or T flipflops are substituted where appropriate, and the resulting equations are minimized accordingly.vThe Logic Synthesizer also synthesizes equations for flipflops to implement state registers of state machines. An equation for each state bit is optimally implemented with either a D or T flipflop. If no state bit assignments have been made, or if an incomplete set of state bit assignments has been created, the Logic Synthesizer automatically creates a set of state bits to encode the state machine. These encodings are chosen to minimize the resources used.v返回 Fitter（适配器）vThe Compiler module that fits the logic of a project into one or more devices. vUsing the database updated by the Partitioner, the Fitter matches the logic requirements of the project with the available resources of one or more devices. It assigns each logic function to the best logic cell location and selects appropriate interconnection paths and pin assignments.vThe Fitter attempts to match any resource assignments made for the project with the resources on the device. If it cannot find a fit, the Fitter allows you to override some or all of your assignments or terminate compilation.vThe Fitter module generates a Fit File that documents pin, buried logic cell, chip, clique, and device assignments made by the Fitter module in the last successful compilation. Each time the project compiles successfully, the Fit File is overwritten. You can back-annotate the assignments in the file to preserve them in future compilations. v返回 Timing SNF Extractor(时序SNF文件提取器)vThe Compiler module that creates a timing SNF containing the logic and timing information required for timing simulation, delay prediction, and timing analysis.vThe Timing SNF Extractor is turned on with the Timing SNF Extractor command (Processing menu). It is also turned on automatically when you turn on the EDIF Netlist Writer, Verilog Netlist Writer, or VHDL Netlist Writer command (Interfaces menu). The Timing SNF Extractor cannot be turned on at the same time as the Functional SNF Extractor or the Linked SNF Extractor.vA timing SNF describes the fully optimized circuit after all logic synthesis and fitting have been completed. Regardless of whether a project is partitioned into multiple devices, the timing SNF describes a project as a whole. Therefore, timing simulation and timing analysis (including delay prediction) are available only for the project as a whole. Neither timing simulation nor functional testing is available for individual devices in a multi-device project. Functional testing is available only for a single-device project.v返回 Assembler（汇编器）vThe Compiler module that creates one or more programming files for programming or configuring the device(s) for a project. vThe Assembler module completes project processing by converting the Fitter's device, logic cell, and pin assignments into a programming image for the device(s), in the form of one or more POFs, SOFs, Hex Files, TTFs, Jam Files, JBC Files, and/or JEDEC Files. POFs and JEDEC Files are always generated; SOFs, Hex Files, and TTFs are always generated if the project uses ACEX 1K, FLEX 6000, FLEX 8000 or FLEX 10K devices; and Jam Files and JBC Files are always generated for MAX 9000, MAX 7000B, MAX 7000AE or MAX 3000A projects. If you turn on the Enable JTAG Support option in the Classic & MAX Global Project Device Options dialog box (Assign menu) or the Classic & MAX Individual Device Options dialog box, the Assembler will also generate Jam Files and JBC Files for MAX 7000A or MAX 7000S projects. After compilation, you can also use SOFs to create different types of files for configuring FLEX 6000, FLEX 8000 and FLEX 10K devices with Convert SRAM Object Files (File menu).vThe programming files can then be processed by the MAX+PLUS II Programmer and the MPU or APU hardware to produce working devices. Several other programming hardware manufacturers also provide programming support for Altera devices. v返回 Simulation Mode vFunctionalSimulates the behavior of flattened netlists extracted from the design files. You can use Tcl commands and scripts to control simulation and to provide vector stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec), although the Simulator uses only the sequence of logic level changes, and not their timing, from the vector stimuli. This type of simulation also allows you to check simulation coverage (the ratio of output ports actually toggling between 1 and 0 during simulation, compared to the total number of output ports present in the netlist).vTimingUses a fully compiled netlist that includes estimated or actual timing information. You can use Tcl commands and scripts to control simulation and to provide vector stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec). This type of simulation also allows you to check setup and hold times, detect glitches, and check simulation coverage (the ratio of output ports actually toggling between 1 and 0 during simulation, compared to the total number of output ports present in the netlist).vTiming using Fast Timing ModelPerforms a timing simulation using the Fast Timing Model to simulate fastest possible timing conditions with the fastest device speed grade 。