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1、 PCI Express Card Electromechanical Specification Revision 1.1 March 28, 2005 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1 2 Revision Revision History Date 1.0 Initial release. 7/22/02 1.0a Incorporated WG Errata C1-C7 and E1. 4/15/03 1.1 Incorporated approved Errata and ECNs. 03/28/05
2、 PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office t
3、o obtain the latest revision of the specification. Questions regarding this specification or membership in PCI-SIG may be forwarded to: Membership Services E-mail: administration Phone: 503-291-2569 Fax: 503-297-1090 Technical Support techsupp DISCLAIMER This PCI Express Card Electromechanical Speci
4、fication is provided “as is” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary
5、 rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI Express is a trademark of PCI-SIG. All other product names are trademarks, registered trademarks, or service marks of th
6、eir respective owners. Copyright 2002-2005 PCI-SIG PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1 3 Contents 1. INTRODUCTION7 1.1. TERMS AND DEFINITIONS.7 1.2. REFERENCE DOCUMENTS .9 1.3. SPECIFICATION CONTENTS.9 1.4. OBJECTIVES.10 1.5. ELECTRICAL OVERVIEW .10 1.6. MECHANICAL OVERVIEW.11
7、 2. AUXILIARY SIGNALS13 2.1. REFERENCE CLOCK.14 2.1.1. Low Voltage Swing, Differential Clocks 14 2.1.2. Spread Spectrum Clocking (SSC).15 2.1.3. REFCLK AC Specifications16 2.1.4. REFCLK Phase Jitter Specification.19 2.2. PERST# SIGNAL 20 2.2.1. Initial Power-Up (G3 to L0).20 2.2.2. Power Management
8、States (S0 to S3/S4 to S0)21 2.2.3. Power Down.22 2.3. WAKE# SIGNAL 24 2.4. SMBUS (OPTIONAL).27 2.4.1. Capacitive Load of High-power SMBus Lines.27 2.4.2. Minimum Current Sinking Requirements for SMBus Devices28 2.4.3. SMBus “Back Powering” Considerations.28 2.4.4. Power-on Reset 28 2.5. JTAG PINS (
9、OPTIONAL).29 2.6. AUXILIARY SIGNAL PARAMETRIC SPECIFICATIONS.30 2.6.1. DC Specifications.30 2.6.2. AC Specifications .31 3. HOT INSERTION AND REMOVAL33 3.1. SCOPE 33 3.2. PRESENCE DETECT33 4. ELECTRICAL REQUIREMENTS.35 4.1. POWER SUPPLY REQUIREMENTS 35 4.2. POWER CONSUMPTION36 4.3. POWER SUPPLY SEQU
10、ENCING37 4.4. POWER SUPPLY DECOUPLING38 4.5. ELECTRICAL TOPOLOGIES AND LINK DEFINITIONS38 4.5.1. Topologies38 4.5.2. Link Definition40 4.6. ELECTRICAL BUDGETS41 4.6.1. AC Coupling Capacitors42 4.6.2. Insertion Loss Values (Voltage Transfer Function).42 4.6.3. Jitter Values44 4.6.4. Crosstalk.46 4.6.
11、5. Lane-to-Lane Skew.46 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1 4 4.6.6. Equalization .47 4.6.7. Skew within the Differential Pair.47 4.7. EYE DIAGRAMS AT THE ADD-IN CARD INTERFACE.47 4.7.1. Add-in Card Transmitter Path Compliance Eye-Diagram 48 4.7.2. Add-in Card Minimum Receiver
12、 Path Sensitivity Requirements49 4.7.3. System Board Transmitter Path Compliance Eye Diagram.50 4.7.4. System Board Minimum Receiver Path Sensitivity Requirements52 5. CONNECTOR SPECIFICATION.53 5.1. CONNECTOR PINOUT53 5.2. CONNECTOR INTERFACE DEFINITIONS.58 5.3. SIGNAL INTEGRITY REQUIREMENTS AND TE
13、ST PROCEDURES 62 5.4. CONNECTOR ENVIRONMENTAL AND OTHER REQUIREMENTS 65 5.4.1. Environmental Requirements.65 5.4.2. Mechanical Requirements67 5.4.3. Current Rating Requirement68 5.4.4. Additional Considerations69 6. ADD-IN CARD FORM FACTORS AND IMPLEMENTATION71 6.1. ADD-IN CARD FORM FACTORS.71 6.2.
14、CONNECTOR AND ADD-IN CARD LOCATIONS.81 6.3. CARD INTEROPERABILITY87 ACKNOWLEDGEMENTS 89 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1 5 Figures FIGURE 1-1: VERTICAL EDGE-CARD CONNECTOR.11 FIGURE 1-2: EXAMPLE SERVER I/O BOARD WITH PCI EXPRESS SLOTS ON A RISER.12 FIGURE 2-1: DIFFERENTIAL
15、REFCLK WAVEFORM .14 FIGURE 2-2: EXAMPLE REFERENCE CLOCK SOURCE TERMINATION15 FIGURE 2-3: SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING .17 FIGURE 2-4: SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT17 FIGURE 2-5: SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCH
16、ING.18 FIGURE 2-6: DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD 18 FIGURE 2-7: DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME18 FIGURE 2-8: DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK.18 FIGURE 2-9: REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING.19 FIGURE 2-10: POWER UP21 FIGURE 2-11: POWER MANAGEMENT STATES.22 FIGURE 2-12: OUT-OF-TOLERANCE THRESHOLD WINDOWS.23 FIGURE 2-13: POWER DOWN.23 FIGURE 2-14: WAKE# RISE AND FALL TIME MEASUREMENT POINTS.31 FIGURE 3-1:
