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1、PFC Training Delta UPS/Industrial Brian Wang July/25/2013 1 OUTLINE PFC topologies Differences between UC3854A and UCC3818A Design for UCC3818A Design tips of CCM PFC 2 PFC Topologies 3 4 Boost PFC Converters 5 Peak Current-Mode Control Ids Vout Vin Poor THD 6 Peak Current-Mode Control Poor PF OVP(8
2、V)/EN(1.9V) RSET(pin12): Oscillator charging current and multiplier limit set CAI (Pin4): CA non-inverting input CT (Pin14): Oscillator timing capacitor 31 PFC IC: UCC3818A DRVOUT (Pin16): Totem-pole MOSFET driver PKLMT (Pin 2): PFC peak current limit 32 PFC IC: UCC3818A 33 PFC IC: UCC3818A 34 PFC I
3、C: UCC3818A PIN 8 (VFF): The RMS voltage signal generated at this pin by mirroring of the IIAC into a single pole external filter. At low line, the VFF voltage should be 1.4V 5.5V CMOS output 35 PFC IC: UCC3818A 20mA Pin 10 (OVP/EN): A window comparator input that disable the output driver if the bo
4、ost Output voltage is a programmed level above the nominal. 1.9V/8V 36 PFC IC: UCC3818A A resistor between 10KR and 100KR is recommended. 37 PFC IC: UCC3818A 10uA 7.5V 38 PFC IC: UCC3818A F=(0.6/(RTxCT) 18V 39 PFC IC: UCC3818A 18 V 1 8 V 40 PFC IC: UCC3818A The current into the IAC is mirrored inter
5、nally to the VFF pin where its filtered to Produce a voltage feed forward signal proportional to line voltage. VFF is for Power limiting IMOUT 1. Keep gain constant 2. Provide input power limit VVAOUT VFF 41 Design STEP PFC Design 42 PFC Design ;Vin=80V RMSinPKin RMSin OUT RMSin II V P I Notes _ min
6、_ _ 2 : = = 43 PFC Design 44 PFC Design Energy balancing equation 45 PFC Design 46 PFC Design 5.0X0.2=1V 47 PFC Design 48 PFC Design 5.6X0.2=1.12V (1.12X10K)/7.5=1.49K 49 PFC Design 50 PFC Design 7. Multiplier setup RVFF. IMOUT is the output current, K=1, Iac is the input current, VFF is the feedfor
7、ward voltage and VVAOUT is the output of VEA. 51 PFC Design Because the VFF voltage is generated from line voltage it needs to be adequately Filtered to reduce total harmonic distortion caused by the 120Hz rectified line voltage A single pole filter was adequate for this design. See page 10 for deta
8、il 52 PFC Design RVFF CVFF 53 PFC Design 0.5 =K mA V 764 5 . 0 382 Use a combination of lower value resistors connected in series to Give the require resistance and distribute the high voltage amongst the resistors. For example two 383KOhm resistors were used in series. RIAC 54 PFC Design 55 PFC Des
9、ign IMOUT(max) for this design is approximately 315uA. The RMOUT resistor can then be determined by In this example VRSENSE was selected to give a dynamic operating range of 1.25V, which gives an RMOUT of roughly 3.91KOhm =K uA V I V R MOUT RSENSE MOUT 91. 3 315 25. 1 (max) Rset selection. Max IMOUT
10、 occurs at the input voltage Peak at low line(Iac= Vin(pk)/RIac=0.157mA) = = - = KChooseK I V R uAII V VIK I ac set MOUTac FF AOacm MOUT 1055. 9 2 3 315;2 ) 1( (min) max,(min)2 56 PFC Design 57 PFC Design pF KK CT CTRT f600 10010 6 . 0 ; 6 . 0 = = pF f R C nF KKfR C KRGRKR mK RV LVf G s f P cf Z IEA
11、fI sout Sci EA 260 2 2 1 1 1025.122 1 2 1 25.12,9 . 3 141. 3 2 . 0400 124102 = = = = = = = = = Setting the crossover freq of the system to 1/10th of the Switching frequency, or 10KHz. GEA is the current amplifier gain Current loop: 58 PFC Design 58 59 PFC Design The bandwidth of the voltage control
12、loop is so small To keep the input distortion to a minimum rather than stability Loop bandwidth must be low enough to attenuate the 2nd harmonic of the line frequency on the output capacitor Voltage loop: 60 PFC Design )(84. 1 4004501202 250 2 , amplitudeV uVCf P V OOr IN pkO = = = Output ripple Vol
13、tage. Amplifier output ripple voltage and gain 0326. 0 % 4,51 , = = = pkO VAOUT VA VAOUTVAOUT V RippleV G VVVV 61 PFC Design Feedback network values, RIN is arbitrary. It must be low enough so that the OP Amp bias currents will not have a large effect on the output, and it must be High enough for a
14、small power dissipation uF KGRf C aroundmWKR vavir f IN 08. 0 0326. 05111202 1 2 1 )300(511 = = = = Set DC output Voltage = - = + =K V K R RR R V V D DIN D OUT REF 76. 9 5 . 7400 5 . 7511 , 62 PFC Design f VI Z fVI f VI fOUTINOUTVAOUT IN VI IN R f C K nCf R Hzf CCRVV P f aroundmWKR = = = = = = = 10
15、2 1 105 801 .192 1 2 1 1 .19, 2 )300(511 2 2 63 PFC Design Design Tips of PFC 64 Contents: PFC Design Tips The worst case condition of Boost PFC Power MOSFET in parallel Design Tips of PFC The worst case condition of Boost PFC in Continous Current Mode SMPS 600V SiC 500/600V CoolMOS CP Fast Switchin
16、g Diode / MOSFET Best RDSON per footprint/ package outline Universal input / High Power Density hence high efficiency requirements due to thermal conditions Low RDSON CCM Mode High Frequency FOM RDSON x COSS Low Qrr diode is a must L1 T1 R1 R2 C OUT RSense V OUT = 400V DC VIN = 85V .265V AC EMI Filter R3 GATE GND VSENSE ISENSE C1 C2 R4 C3 VCOMP IC
