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1、2.1 CMOS制造工艺流程简介,We will describe a modern CMOS process flow. Process described here requires 16 masks and 100 process steps.,1,第二章 CMOS制备基本流程,Stages of IC Fabrication,2, In the simplest CMOS technologies, we need to realize simply NMOS and PMOS transistors for circuits like those illustrated below.
2、,CMOS Digital Gates,反相电路,或非门：同时输入低电平时才能获得高电平输出,3,PMOS and NMOS wafer cross section after fabrication,2-Level Metal CMOS,两层互连布线的CMOS,4,有源器件（MOS、BJT等类似器件），必须在外加适当的偏置电压情况下，器件才能正常工作。,对于MOS管，有源区分为源区和漏区，在进行互联之前，两者没有差别。, ,Choosing a Substrate Active Region N and P Well Gate Tip or Extension Source and Drai
3、n Contact and Local Interconnect Multilevel Metalization,Processing Phases,5,1 m Photoresist,40 nm SiO2,Choose the substrate (type, orientation, resistivity, wafer size), Initial processing:,- Wafer cleaning - thermal oxidation, H2O ( 40 nm, 15 min. 900C) - nitride LPCVD (低压化学气相沉积) ( 80 nm 800C), Su
4、bstrate selection: - moderately high resistivity (25-50 ohm-cm) - (100) orientation - P- type.,80 nm Si3N4,Choosing a Substrate,Si,(100), P Type,2550cm,1st Mask Photoresist spinning and baking 100C ( 0.5 - 1.0 m),6,2.2 有源区的形成, Photolithography - Mask #1 pattern alignment and UV exposure - Rinse away
5、 non-pattern PR - Dry etch the Nitride layer - Plasma etch with Fluorine CF4 or NF4 Plasma - Strip Photoresist (H2SO4或O2 plasma),Active Area Definition (主动区),SiO2,Si3N4,Photoresist,7, Wet Oxide (thick SiO2) - H2O ( 500 nm, 90 min. 1000C), Strip Nitride layer - Phosophoric acid (磷酸) or plasma etch，选择
6、性问题,Field Oxide Growth,- LOCOS: Local Oxidation of Silicon (局部硅氧化工艺),SiO2,Si3N4, 薄的SiO2层，厚的Si3N4层，避免鸟喙(birds beak)的影响,8, 场区:很厚的氧化层，位于芯片上不做晶体管、电极接触的区域，可以起到隔离晶体管的作用。, Photolithography (套刻) - Mask #2 pattern alignment and UV exposure, Ion Implantation 离子注入 - B+ ion bombardment,Penetrate thin SiO2 and f
7、ield SiO2 - 反型：半导体表面的少数载流子浓度等于体内的多数载流子浓度时，半导体表面开始反型。 - 150-200 keV for 1013cm-2 - Implantation Energy and total dose adjusted for depth and concentration,P-well Fabrication, Strip Photoresist,- Rinse away non-pattern PR,2.3 N阱和P阱的形成,SiO2,Photoresist,9, Ion Implantation - P+ ion bombardment,- Penetra
8、te thin SiO2 and field SiO2 - 300-400 keV for 1013cm-2 - Implantation Energy and,total dose adjusted for depth and concentration, Strip Photoresist,N-well Fabrication, Photolithography - Mask #3 pattern alignment and UV exposure - Rinse away non-pattern PR,10, Thermal Anneal (热退火) - Repair crystal l
9、attice structure damage due to implantation, Dry Furnace (N2 ambient，防止氧化层生成) - Anneal 30 min 800C or RTA(快速热退火) 10 sec 1000C,- Drive-in 4-6 hours 1000 C - 1100 C,Thermal Anneal and Diffusion, N and P Drive-in (扩散推进) - Thermal diffusion of dopant to shallower than desired depth - Drive-in is a cumul
10、ative process!,11, Photolithography - Mask #4 pattern alignment and UV exposure - Rinse away non-pattern PR,- B+ ion bombardment - 50-75keV for 1-5 1012cm-2,- Implantation Energy and total dose adjusted for depth and concentration, Strip Photoresist,Threshold Adjustment, P-type NMOS, Ion Implantatio
11、n,2.4 栅电极的制备,开启电压调整,12,调整之前P阱的掺杂浓度,调整时的注入剂量,Threshold Adjustment, N-type PMOS, Photolithography - Mask #5 pattern alignment and UV exposure - Rinse away non-pattern PR,- As+ ion bombardment - 75-100keV for 1-5 1012cm-2,- Implantation Energy and total dose adjusted for depth and concentration, Strip
12、Photoresist, Ion Implantation,13, Remove existing gate region oxide, Furnace Steps - Thermal Anneal,- Oxide growth 3-5 nm - O2 ambient - 0.5-1 hour 800C,Gate Oxide Growth 栅极氧化层生长,- HF etch，具有良好的选择性,- Dry Furnace (N2 ambient) - 30 min 800C,14, LPCVD Deposition of Si - Silane 硅烷, Amorphous or polycrys
13、talline,silicon layer results,Ion Implantation - P+ or As+ (N+) implant dopes the poly (typically 5 1015 cm-2),Polysilicon Gate Deposition, 0.3-0.5 um,SiO2,多晶硅薄膜,15,热分解, Photolithography - Mask #6 pattern alignment and UV exposure, Plasma Etch - Anisotropic etch 各向异性蚀刻 - Vertical etch rate high,- La
14、teral etch rate low,Gate Patterning （栅极的图形化）,- Rinse away non-pattern PR, Clorine (氯)or Bromine (溴) based for SiO2 selectivity,16,目标：,NMOS器件中的N-注入区,PMOS器件中的P-注入区,多晶硅栅的两侧形成侧壁隔离层的薄氧 化层,2.5 前端或延伸区(LDD)的形成,17,LDD:, Lightly Doped Drain (轻掺杂漏) Reduce short channel effects due to gate voltage magnitudes an
15、d electric fields Source and Drain must be layered as NMOS:N+ N- P or PMOS: P+ P- N,Extension (LDD) Formation NMOS, Photolithography - Mask #7 pattern alignment and UV exposure - Rinse away non-pattern PR,- P+ ion bombardment - 50keV for 5 1013cm-2, Strip Photoresist, Ion Implantation,18, Photolithography Mask #8 pattern alignment,and UV exposure Rinse away non-pattern PR Ion Implantation B+ ion bombardment 50 keV for 5 1013cm-2, Strip Photoresist,Extension (LDD) Formation PMOS,19,SiO2 隔离介质层,CVD or LPCVD Deposition of SiO2, Silane and Oxygen,Or,0.5 um, Provides spacing between g
