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硬件接口定义规范-III

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10.PCI 是 Peripheral Component Interconnect 的缩写接口卡的外观PCI 标准 32 位/64 位 接口卡----------------------------------------------------------------| PCI 元件侧 (B 面) || || || || ____ 32 位引脚部分 64 位引脚部分 ___||___| |||||||--|||||||||||||||||--|||||||--||||||||||||||^ ^ ^ ^ ^ ^ ^ ^b01 b11 b14 b49 b52 b62 b63 b94PCI 5V 32/64位卡| optional || ____ 32 位引脚部分 64 位引脚部分 ___||___| ||||||||||||||||||||||||||--|||||||--||||||||||||||PCI 3.3V 32/64位卡| optional || ____ 32 位引脚部分 64 位引脚部分 ___||___| |||||||--||||||||||||||||||||||||||--||||||||||||||Pin +5V +3.3V Universal DescriptionA1 TRST     Test Logic ResetA2 +12V     +12 VDCA3 TMS     Test Mde SelectA4 TDI     Test Data InputA5 +5V     +5 VDCA6 INTA     Interrupt AA7 INTC     Interrupt CA8 +5V     +5 VDCA9 RESV01     Reserved VDCA10 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)A11 RESV03     Reserved VDCA12 GND03 (OPEN) (OPEN) Ground or Open (Key)A13 GND05 (OPEN) (OPEN) Ground or Open (Key)A14 RESV05     Reserved VDCA15 RESET     ResetA16 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)A17 GNT     Grant PCI useA18 GND08     GroundA19 RESV06     Reserved VDCA20 AD30     Address/Data 30A21 +3.3V01     +3.3 VDCA22 AD28     Address/Data 28A23 AD26     Address/Data 26A24 GND10     GroundA25 AD24     Address/Data 24A26 IDSEL     Initialization Device SelectA27 +3.3V03     +3.3 VDCA28 AD22     Address/Data 22A29 AD20     Address/Data 20A30 GND12     GroundA31 AD18     Address/Data 18A32 AD16     Address/Data 16A33 +3.3V05     +3.3 VDCA34 FRAME     Address or Data phaseA35 GND14     GroundA36 TRDY     Target ReadyA37 GND15     GroundA38 STOP     Stop Transfer CycleA39 +3.3V07     +3.3 VDCA40 SDONE     Snoop DoneA41 SBO     Snoop BackoffA42 GND17     GroundA43 PAR     ParityA44 AD15     Address/Data 15A45 +3.3V10     +3.3 VDCA46 AD13     Address/Data 13A47 AD11     Address/Data 11A48 GND19     GroundA49 AD9     Address/Data 9A52 C/BE0     Command, Byte Enable 0。

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