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1、 Avalanche Characteristics and Ratings of Power MOSFET Giovanni Privitera Product as soon as the current grows, it begins to interest also the p, lighter doped, regions. Since, by design, the value of lateral resistance Rp is higher than the one of the vertical resistance of the heavy doped p+ regio
2、n, and the current is concentrated in the region p+, so the BJT should not turn on. As soon as the current begins to interest the p region, causing a sufficient drop of voltage to equal the VBE of the BJT, the current of the base, Ib, in conjunction with the of the transistor will cause the BJT turn
3、-on. VBE has a negative temperature coefficient consequently leading to thermal runaway and finally, the destruction of the device due to the secondary breakdown of the parasitic BJT. The adoption of a strongly doped P+ region, determining the reduction of the gain of the transistor and the base res
4、istance has been the first step for the improvement of the MOSFET, followed by other more subtle optimizations. The power that is dissipated in the MOSFET causes an increase in junction temperature. If the temperature increases to a critical value set by the property of the silicon 2, the failure, w
5、ithout the contribution of the parasitic bipolar, occurs because of the creation of thermally generated carriers in the epitaxyal / bulk region and so the creation of hot spots. The critical temperature to have this phenomenon is beyond the maximum junction temperature of the devices and is related
6、to the intrinsic temperature of doped silicon, to which the concentration of the bulk equals the one of the thermal generated carriers. The temperature increase during avalanche phenomena, due to thermal capacitance of the silicon, is not instantaneous. Hence, this kind of failure should be distingu
7、ished from that caused by current as the device holds the breakdown voltage for a finite time before destruction. 1.3 Testing the Avalanche Ruggedness The Avalanche capability of the device is classically evaluated by a circuit that performs an Unclamped Inductive Switching (UIS) like the one descri
8、bed in Figure 2. Figure 2 UIS reference diagram The operation is the following; at zero time the device switches on, closing the circuit. Due to the presence of an inductance, (considering some resistance due to the layout and the ON resistance of the MOSFET) the current increases following an R Ava
9、lanche characteristics and ratings of Power MOSFET 3 exponential law, as a function of the L / R characteristics of the circuit. Figure 3 Typical UIS waveforms As soon as the device is switched off, as the magnetic field in the inductance cannot instantaneously go to zero, the di/dt causes an over v
10、oltage on the drain of the device. Naturally, the device is practically an open circuit up to its own blocking voltage, therefore the extra voltage is limited by the BVDSS of the DUT. During the avalanche, the current flows through the DUT, dissipating the accumulated energy that was stored in the c
11、oil during the charging. Table 1 explains several relations for the tav, Eav and the Pavg with several circuit configurations. Figure 4 Constant current avalanche fixture A device is commonly defined rugged, or avalanche-rated, if at some stated conditions of coil and conducted current it survives t
12、his test. In the past, other circuits were suggested to test this device capability like the one in Figure 4. The current is maintained constant for a set time eliminating the dependency for the energy to be withstood on the coil, but actually the only recognized method (JEDEC standard No. 24-5, MIL
13、- STD750D method 3040.2) is the circuit described in Figure 2. + - VDD ZENER DUT L + - VDD ZENER DUT L Figure 5 disconnected supply UIS fixture A circuit commonly used to test the Avalanche ruggedness of the MOSFET is shown in figure 5. It has a special feature of a power switch in series to the VDD
14、 that connects the voltage source to the circuit only during the coil charging, disconnecting it a few microseconds before the switch-off and the avalanche operation. This technique allows to increase the Vdd beyond its maximum rated VDS, speeds up the charge of the coil during turn on, and conseque
15、ntly decreases the turn on state time. Also, the energy dissipated is different as one can read in the table 1. 1.4 Datasheet Ratings When the device is classified as “Avalanche Rated”, the datasheet provides the end-user some useful parameters, which define the ratings of the device during avalanch
16、e: -Iar, defined as the maximum current that can flow through the device during the avalanche operations without any BJT latching phenomenon. This Maximum limit must be considered as an absolute maximum rating. Even if the critical current to bring the device to failure is higher than the IAR, the producer guarantees the operation of the device below this limit. Besides, it is usually tested for several microseconds. All STMicroelectronics High Voltage Power MOSFET are tested according
