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1、2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer CY29949 Cypress Semiconductor Corporation3901 North First StreetSan Jose,CA 95134408-943-2600 Document #: 38-07289 Rev. *D Revised November 6, 2003 Features 2.5V or 3.3V operation 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS-/LVT
2、TL-compatible outputs 15 clock outputs: drive up to 30 clock lines 1X and 1/2X configurable outputs Output three-state control 350 ps max. output-to-output skew Pin compatible with MPC949, MPC9449 Available in Commercial and Industrial temp. range 52-pin TQFP package Description The CY29949 is a low
3、-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 15
4、 outputs are LVCMOS or LVTTL compatible and can drive 50 series or parallel termi- nated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:30. The CY29949 is capable of generating 1X and 1/2X signals from
5、a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:D) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs. The CY29949 outputs can also be three-stated via the MR/OE# input. When MR/OE# is set HIGH, it resets
6、 the internal flip-flops and three-states the outputs. Block Diagram Pin Configuration MR/OE# TCLK_SEL VDD TCLK0 TCLK1 PECL_CLK PECL_CLK# PCLK_SEL DSELA DSELB DSELC DSELD VSS NC VDDC QD4 VSS QD3 VDDC QD2 VSS QD1 VDDC QD0 VSS NC NC VDDC QB2 VSS QB1 VDDC QB0 VSS VSS QA1 VDDC QA0 VSS NC VSS QC0 VDDC QC
7、1 VSS QC2 VDDC QC3 VSS VSS QD5 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 CY29949 0 1 1 2 0 1 1 2 0 1 0 1 DSELA DSELB DSELC DSELD MR/OE# 1 2 1 2 0 1 0 1 2 3 4 6 QA(0:1) QB(0:2) QC(0:3) QD(0:5)
8、PECL_SEL TCLK_SEL PECL_CLK PECL_CLK# R R R R 元器件交易网w w w . c e c b 2 b . c o m CY29949 Document #: 38-07289 Rev. *DPage 2 of 7 Note: 1. PD = internal pull-down, PU = internal pull-up. Pin Description1 PinNamePWRI/ODescription 6PECL_CLKI, PDPECL Input Clock 7PECL_CLK#I, PUPECL Input Clock 4, 5TCLK(0,
9、1)I, PUExternal Reference/Test Clock Input 49, 51QA(1,0)VDDCOClock Outputs 42, 44, 46QB(2:0)VDDCOClock Outputs 31, 33, 35, 37QC(3:0)VDDCOClock Outputs 16, 18, 20, 22, 24, 28 QD(5:0)VDDCOClock Outputs 9, 10, 11, 12DSEL(A:D)I, PDDivider Select Inputs. When HIGH, selects 2 input divider. When LOW, sele
10、cts 1 input divider. 2TCLK_SELI, PDTCLK Select Input. When LOW, TCLK0 clock is selected and when HIGH TCLK1 is selected. 8PCLK_SELI, PDPECL Select Input. When HIGH, PECL clock is selected and when LOW TCLK(0,1) is selected 1MR/OE#I, PDOutput Enable Input. When asserted LOW, the outputs are enabled a
11、nd when asserted HIGH, internal flip-flops are reset and the outputs are three-stated. If more than 1 bank is being used in /2 mode, a reset must be performed (MR/OE# asserted high) after power-up to ensure that all internal flip flops are set to the same state. 17, 21, 25, 32, 36, 41, 45, 50 VDDC2.
12、5V or 3.3V Power Supply for Output Clock Buffers 3VDD2.5V or 3.3V Power Supply 13, 15, 19, 23, 29, 30, 34, 38, 43, 47, 48, 52 VSSCommon Ground 14, 26, 27, 39, 40, NCNot Connected 元器件交易网w w w . c e c b 2 b . c o m CY29949 Document #: 38-07289 Rev. *DPage 3 of 7 Maximum Ratings2 Maximum Input Voltage
13、Relative to VSS: VSS 0.3V Maximum Input Voltage Relative to VDD:.VDD + 0.3V Storage Temperature: 65C to + 150C Operating Temperature:40C to +85C Maximum ESD Protection.2 kV Maximum Power Supply: 5.5V Maximum Input Current: 20 mA This device contains circuitry to protect the inputs against damage due
14、 to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS (Vin or Vout) VDD Unused inputs must always be tied
15、to an appropriate logic voltage level (either VSS or VDD). DC Parameters (VDD = VDDC = 3.3V 10% or 2.5V 5%, over the specified temperature range) ParameterDescriptionConditionsMin.Typ.Max.Unit VILInput Low VoltageVDD = 3.3V, PECL_CLK single ended1.491.825V VDD = 2.5V, PECL_CLK single ended1.101.45 A
16、ll other inputsVSS0.8 VIHInput High VoltageVDD = 3.3V, PECL_CLK single ended 2.1352.42V VDD = 2.5V, PECL_CLK single ended1.752.0 All other inputs2.0VDD IILInput Low Current3100A IIHInput High Current3100 VPPPeak-to-Peak Input Voltage PECL_CLK 3001000mV VCMRCommon Mode Range4 PECL_CLK VDD = 3.3VVDD 2.0VDD 0.6V VDD = 2.5VVDD 1.2VDD 0.6 VOLOutput Low Voltage5IOL = 20 mA0.4V VOHOutput High Voltage5IOH = 20 mA, VDD = 3.3V
