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1、1 DFT_Compiler 使用说明使用说明 摘要摘要：本文档介绍了 DFT_Compiler 的基本使用，分基本流程框图和基本操作内 容两部分，二者是相互对应的，流程框图是对整个过程的总体说明，操作内容是 是对过程的具体实现以及对为什么要进行对应过程的基本解释。 一一、基本流程基本流程框图框图 2 二二、基本操作内容基本操作内容 I. Preparing to Run DFT Compiler Before running DFT Compiler, you need to set up your interface, prepare your design environment, an
2、d read in your design. This section covers the following topics: Invoking the Synthesis Tool Setting Up Your Design Environment Reading In Your Design Setting the Scan Style Configuring the Test Cycle Timing Defining the DFT Signals 1. Invoking the Synthesis Tool You can use DFT Compiler from within
3、 any of the following synthesis tools: * Design Compiler * Design Vision * DC Explorer 2. Setting Up Your Design Environment To set up your design environment, you need to define the paths for the logic libraries and designs you are using, and define any special reporting parameters. # configure log
4、ic libraries set search_path /lib_path #注意对库路径的正确设置 set target_library library.db set link_library * library.db #注意*号不能丢，且其后有空格 3. Reading In Your Design To read in your design, specify the appropriate file read commands depending on the file format: read_ddc, read_verilog, read_vhdl. The following
5、example reads in a list of Verilog files: read_verilog /top_path/top.v /block_path/block.v #注意对设计路径的正确设置 Use the current_design and link commands to link the top level of the current design: current_design top link If DFT Compiler is unable to resolve any references, you must provide the missing des
6、igns before proceeding. After linking, use the read_sdc command (or the source command) to apply the design constraints: read_sdc top_constraints.sdc Note: If you read in the top-level design in the Synopsys logic database (.ddc) format, the design constraints might already be applied. 4. Setting th
7、e Scan Style DFT Compiler uses the selected scan style to perform scan synthesis. A scan style dictates the appropriate scan cells to insert during optimization. This scan style is used on all modules of your design. 3 set_scan_configuration -style multiplexed_flip_flop The default style is multiple
8、xed flip-flop. To specify another scan style, use the style option of the set_scan_configuration command. For example, set_scan_configuration -style clocked_scan 5. Configuring the Test Cycle Timing（*） Set the test timing variables to the values required by your ASIC vendor. If you are using TetraMA
9、X ATPG to generate test patterns, and your vendor does not have specific requirements, the default settings produce the best results: set_app_var test_default_delay 0 set_app_var test_default_bidir_delay 0 set_app_var test_default_strobe 40 set_app_var test_default_period 100 These are the default s
10、ettings; you do not need to add them to your script. 6. Defining the DFT Signals Most DFT Compiler commands include the concept of a view, specified with the view option. The valid view values are: * -view existing_dft The existing DFT view is descriptive and describes an existing signal network. An
11、 example is an existing functional clock signal that is also used as a scan clock in test mode. * -view spec The specification view is prescriptive and describes action that must be taken during DFT insertion. It indicates that the signal network does not yet exist, and the insert_dft command must a
12、dd it. An example is a scan-enable signal network that must be routed to all scannable flip-flops during DFT insertion. A view is typically specified in scan specification commands, such as set_dft_signal. When performing scan synthesis, you use a combination of the two views. When you define existi
13、ng signals that are used in test mode, you use the existing DFT view. When you define the DFT structure you want inserted, you use the specification view. Define any clocks and asynchronous set and reset signals in the existing DFT view: set_dft_signal -view existing_dft -type ScanClock . set_dft_si
14、gnal -view existing_dft -type Reset . If you have a dedicated scan-enable port, define it in the specification view: set_dft_signal -view spec -type ScanEnable -port scan_enable_port -active_state 1 If no scan-enable port is identified, DFT Compiler creates a new scan-enable port. If you are using e
15、xisting ports as scan-in and scan-out ports, define them in the specification view (even if they have existing functional logic connections): set_dft_signal -view spec -type ScanDataIn -port DAT_IN7 . set_dft_signal -view spec -type ScanDataIn -port DAT_IN0 set_dft_signal -view spec -type ScanDataOu
16、t -port DAT_OUT7 . set_dft_signal -view spec -type ScanDataOut -port DAT_OUT0 4 Otherwise, DFT Compiler creates new scan-in and scan-out ports as needed. II. Performing Scan Synthesis The scan synthesis process tests and prepares your RTL design for test-ready compilation, synthesizes it, tests it again, performs scan insertion, and analyzes your post-DFT design. This section covers the following processes: Performing RTL Test Design Rul
