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1、Content IC DESIGN MAGAZINE VOLUME 36www.C 1Apr. 2003 CIC eNew SynTestDFT Memory BIST SynopsysDFT SynopsysScan synthesis SynopsysDFTRTL cell library SynopsysScan synthesis RTL code constraintsscanDFTscript DFT Reprint Copyright 2001 by Chip123 Technology Co., Ltd. All rights reserved ISSN 1609-8633
2、 Reprint Copyright 2001 by Chip123 Technology Co., Ltd. All rights reserved ISSN 1609-8633 IC DESIGN MAGAZINE VOLUME 36 www.C 2Apr. 2003 DFT /* Setup the test timing variables with TetraMAX ATPG */ current_design top test_default_delays = 0 test_default_bidir_delay = 0 test_default_strobe = 40 tes
3、t_default_period = 100 test_default_strobe_width = 1.0 create_test_clock I_CLK -period 100 -waveform 4555 test_default_scan_style = multiplexed_flip_flop set_scan_signal test_scan_enable -port I_SCAN_EN ? ? HDL Design Set constraints/scan style Check design rules Run test-ready compile Check constra
4、ints/design rules Set scan configuration Preview scan, check rules Build scan chains Check constraints/design rules Violations Not met Adjust constraints Adjust constraints Save design, write test protocol Not met Used Tools HDL Compiler Design Compiler DFT Compiler Reprint Copyright 2001 by Chip123
5、 Technology Co., Ltd. All rights reserved ISSN 1609-8633 IC DESIGN MAGAZINE VOLUME 36www.C 3Apr. 2003 scripts test timingdelaybidir_delay test clockstrobestrobe ATEstrobetest cycleclock edgetest protocol strobe-before-clockstrobetest cycleclock edge test protocolstrobe-after-clockTetraMAX ATPGTest
6、 Protocolstrobe-before-clockstrobeclock create_test_clockclockscan ? ? clock input output bidirectionals strobe strobe width ? ? stylemultiplexed_flip_flopFlip-Flopmultiplexer functional inputscan inputset_scan_signal scan enable rtldrc RTL level DFT HDLlog Starting rtldrc . Initializing rtldrc . St
7、arting rule checks . Information: Scan style is multiplexed_flip_flop. (TEST-1212) Information: There are 1 test clocks in the design. (TEST-958) Test clocks are: Reprint Copyright 2001 by Chip123 Technology Co., Ltd. All rights reserved ISSN 1609-8633 IC DESIGN MAGAZINE VOLUME 36 www.C 4Apr. 2003
8、 DFT I_CLK (no_file_info, no_line_info) Information: There are 17 blackboxes in the design. (TEST-959) Registers are: comb/c4msrom0101/BistCtrl_i0/S27/add_39 (no_file_info, no_line_info) . . . . . logscanmultiplexed_flip_floptest clock I_CLK17black boxes compile -scan test-ready compileFlip-Flopscan
9、 Flip-Flop scan elementsscan Flip-Flopscan output scan inputscan insertion check_scanDFTlog Information: Starting test design rule checking. (TEST-222) .full scan rules enabled. .basic checks. Warning: Cell comb/c4msrom0101/WRAPPED_RAM_i0/ROM_i0 (c4msrom0101) is unknown (black box) because functiona
10、lity for output pin O11 is bad or incomplete. (TEST-451) Warning: Cell comb/cpu/regs/dram/c4mtram72x8/WRAPPED_RAM_i0/SRAM_i0 (c4mtram72x8) is unknown (black box) because functionality for output pin DO7 is bad or incomplete. (TEST-451) Warning: Three-state net comb/c4msrom0101/WRAPPED_RAM_i0/O11 is
11、not properly driven. (TEST- 115) Information: Because driver O11 is a three-state pin of black box cell comb/c4msrom0101/WRAPPED_RAM_i0/ROM_i0 (c4msrom0101). (TEST-199) Information: There are 19 other nets with the same violation. (TEST-289) .basic sequential cell checks. .checking combinational fee
12、dback loops. .inferring test protocol. Information: Inferred system/test clock port clk (45.0,55.0). (TEST-260) .simulating parallel vector. .simulating parallel vector. .simulating serial scan-in. .simulating parallel vector. .binding scan-in state. Reprint Copyright 2001 by Chip123 Technology Co.,
13、 Ltd. All rights reserved ISSN 1609-8633 IC DESIGN MAGAZINE VOLUME 36www.C 5Apr. 2003 .binding scan-out state. .simulating serial scan-out. .simulating parallel vector. Information: Test design rule checking completed. (TEST-123) * Test Design Rule Violation Summary Total violations: 22 * MODELING
14、 VIOLATIONS 2 Unknown cell violations (TEST-45x) TOPOLOGY VIOLATIONS 20 Improperly driven three-state net violations (TEST-115) * Sequential Cell Summary 0 out of 182 sequential cells have violations * SEQUENTIAL CELLS WITHOUT VIOLATIONS * 182 cells are valid scan cells ROMSRAMUnknown cell violation
15、sTEST- 451tri-state20violationsTEST-115 TEST199)sequential cellcombinational feedback loopsscan summary violation22TetraMAX violationssequential cell summarysequential cellviolationviolationcellscan chain report_constraint -all_violatorsconstraints constraintscompile strategyscan configurationscan chainscanscrip
