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1、UESTC-Ning Ning1 Chapter 2 Chip Level Interconnection 芯片互连技术 集成电路封装测试与可靠性集成电路封装测试与可靠性 UESTC-Ning Ning2 Wafer In Wafer Grinding (WG研磨研磨) Wafer Saw (WS 切割切割) Die Attach (DA 黏晶黏晶) Epoxy Curing (EC 银胶银胶烘烤烘烤) Wire Bond (WB 引线键合引线键合) Die Coating (DC 晶粒封晶粒封胶胶/涂覆涂覆) Molding (MD 塑封塑封) Post Mold Cure (PMC 模塑后
2、模塑后烘烤烘烤) Dejunk/Trim (DT 去去胶去纬胶去纬) Solder Plating (SP 锡铅电镀锡铅电镀) Top Mark (TM 正面正面印码印码) Forming/Singular (FS 去框去框/成型成型) Lead Scan (LS 检测检测) Packing (PK 包装包装) 典型的典型的IC封装工艺流程封装工艺流程 集成电路封装测试与可靠性集成电路封装测试与可靠性 UESTC-Ning Ning3 电子级硅所含的硅的纯度很高，可 达 99.9999 99999 % 中德电子材料公司制作的晶棒(长度 达一公尺，重量超过一百公斤) 集成电路封装测试与可靠性集成
3、电路封装测试与可靠性 UESTC-Ning Ning4 Wafer Back Grinding Purpose The wafer backgrind process reduces the thickness of the wafer produced by silicon fabrication (FAB) plant. The wash station integrated into the same machine is used to wash away debris left over from the grinding process. Process Methods: 1) C
4、oarse grinding by mechanical. (粗磨粗磨) 2) Fine polishing by mechanical or plasma etching. (细磨抛光细磨抛光) 集成电路封装测试与可靠性集成电路封装测试与可靠性 UESTC-Ning Ning5 旋转及振荡轴旋转及振荡轴 在旋转平盘上在旋转平盘上 之晶圆之晶圆 下压力下压力 工作台仅在指示有晶圆期间才旋转工作台仅在指示有晶圆期间才旋转 Method: The wafer is first mounted on a backgrind tape and is then loaded to the backgri
5、nd machine coarse wheel. As the coarse grinding is completed, the wafer is transferred to a fine wheel for polishing. 集成电路封装测试与可靠性集成电路封装测试与可靠性 UESTC-Ning Ning6 Wafer Back Grinding process Objective: To reduce the thickness with a coarse grinding wheel. Objective: To load and align the wafer into the
6、 wafer cleaning and tape lamination machine. Objective: To clean the wafer for the next lamination step. Objective: To laminate a protective layer of film on the circuitry surface of the wafer . 2. Wafer cleaning 1. Load and Align3. Back grind Tape lamination 4. Coarse grinding 集成电路封装测试与可靠性集成电路封装测试与
7、可靠性 UESTC-Ning Ning7 Wafer Back Grinding process (Cont.) Objective: To unload the wafer from back grinding machine. 5. Fine polishing 6. Unload Objective: To load the wafer to wafer mounter. Objective: To remove the back grind tape after wafer mounted on the frame. 8. Tape removal 7. Load 集成电路封装测试与可
8、靠性集成电路封装测试与可靠性 UESTC-Ning Ning8 Wafer Back Grinding Issues and Challenges Issues Ease of process Thin wafer handling from one step to another Back grinding tape removal Excessive stresses removal or reduction from the wafer.（应力应力） Yield Wafer breakage due to stress built up during thinning process.
9、Scratches.(.(划痕划痕) ) Die metallization smearing.（污点污点，模糊模糊） Equipment stability and capability Challenges Market requirements drive for very thin wafer (3 mils) Flip chip wafer back grinding 集成电路封装测试与可靠性集成电路封装测试与可靠性 UESTC-Ning Ning9 Wafer sawing Wafer Separation Process Purpose: The wafer separation
10、 process is to divide the wafer into individual dice or chips. Process Methods: 1)Sawing (with diamond-impregnated saw blade) 锯切锯切 Single or dual cut Step cut or bevel cut 2) Partial scribing (with laser beam, diamond- tipped scribing tool, or diamond-impregnated saw blade) 局部划片器 集成电路封装测试与可靠性集成电路封装测
11、试与可靠性 UESTC-Ning Ning10 Wafer sawing 集成电路封装测试与可靠性集成电路封装测试与可靠性 UESTC-Ning Ning11 Wafer Sawing is a Front-of-Line (FOL) operation that cuts the wafer along the streets separating the individual die. Streets, also called scribe lines, are lines on the wafer that separate each individual die from the su
12、rrounding dice. Kerf width is the saw width. After the wafer is sawn, the wash station, using a detergent, removes residual cut material from the wafer. Wafer sawing 集成电路封装测试与可靠性集成电路封装测试与可靠性 UESTC-Ning Ning12 切割设备示意图切割设备示意图 晶圆 工作台 刀刃 Dicing Blade Silicon Wafer Blue Tape Flame Flame 两次进刀切割法 集成电路封装测试与
13、可靠性集成电路封装测试与可靠性 UESTC-Ning Ning13 The SAWING process is broken down into four steps: Objective: To rinse slurry (silicon dust) before it dries with de-ionized water and CO2. Also to dry wafer by pinning and with clean air, and unload wafer. 1. Load and Align 2. Pattern Recognition System (PRS) 3. Cu
14、t 4. Wash, Rinse, Dry and Unload Objective: To separate dice from a wafer with resin-bonded diamond wheel. (First blade is used to remove metal structures and stresses on street for second blade.) Wafer sawing 集成电路封装测试与可靠性集成电路封装测试与可靠性 UESTC-Ning Ning14 Wafer Sawing Issues and Challenges Issues: Ease
15、 of process -Die chipping control （碎屑） -Multiple die types and sizes processing Yield -Saw on die -Scratches （划痕） -Chipping -Die crack Equipment stability and capability Challenges: Smaller kerf width for more die per wafer Larger wafer size (300mm) with multiple die types and sizes 集成电路封装测试与可靠性集成电路
16、封装测试与可靠性 UESTC-Ning Ning15 Wire Bonding Technology - Die Attach Process Purpose: The die attach process is to attach the sawed die in the right orientation accurately onto the substrate with a bonding medium in between to enable the next wire bond first level interconnection operation . Process Methods 1)Semi-automated eutectic die attach. 低共熔物芯片粘接低共熔物芯片粘接 2)Fully automated adhesive die attach. 胶粘剂粘接胶粘剂粘接 集成电路封装测试与可靠性集成电路封装测试与可靠性 UES
