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1、部分习题参考答案3.6 习题33.合法标识符：my_counter、Decoder_1、data_BUS、Sig_N非法标识符：2FFT、Sig_#N、Not-Ack、ALL_RST_、return、entity7.参考程序为：entity NOR2a isPort( A,B: in std_logic;C: out std_logic );end NOR2a;15. Q=”00100100”4.4 习题41.用PROCESS语句和CASE-WHEN语句，参考程序如下：library ieee;use ieee.std_logic_1164.all;entity decoder3_8 is p
2、ort(a,b,c,g1,g2a,g2b: in std_logic; y: out std_logic_vector(7 downto 0);end decoder3_8; architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begin dz y y y y y y y yy=XXXXXXXX; end case; else y=11111111; end if; end process;end ;用WHEN-ELSE语句，参考程序如下：architecture a1 of decoder3_8 issi
3、gnal dz:std_logic_vector(2 downto 0);begindz=c&b&a;with dz selectdout=11111110 when 000, 11111101 when 001, 11111011 when 010, 11110111 when 011, 11101111 when 100, 11011111 when 101, 10111111 when 110, 01111111 when 111, XXXXXXXX when others;end a1;2.参考程序如下：entity v74x148 isport ( s: in std_logic;
4、i: in std_logic_vector ( 7 downto 0 ); y: out std_logic_vector ( 2 downto 0 ); yex , ys: out std_logic );end v74x148;architecture behave of v74x148 is begin process ( s , i ) variable j，k: integer range 7 downto 0; variable done: bit; begin done := 0; ys=0; if s = 1 then yex= 1; ys = 1; y = “111”; e
5、lse for j in 7 downto 0 loop if done = 1 then null; elsif i(j) = 0 then done :=1; yex =0; ys=1; k=7-j; y = conv_std_logic_vector (k, 2 downto 0); end if; end loop; end if; end process;end behave;3.参考程序如下：add4的vhdl代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;use ieee.std_logic_arith.all;use ieee.std_l
6、ogic_unsigned.all;ENTITY add4 ISPORT ( a : IN std_logic_vector(3 DOWNTO 0); b : IN std_logic_vector(3 DOWNTO 0); cin : IN std_logic; sum : OUT std_logic_vector(3 DOWNTO 0); g,p : OUT std_logic);END add4;ARCHITECTURE behave OF add4 ISsignal c1,c2,c3,temp0,temp1,temp2,temp3,temp4,temp5:STD_LOGIC;BEGIN
7、sum(0)=a(0) xor b(0) xor cin;sum(1)=a(1) xor b(1) xor c1;sum(2)=a(2) xor b(2) xor c2;sum(3)=a(3) xor b(3) xor c3;c1=(a(0) and b(0) or (a(0) or b(0) and cin);c2=(a(1) and b(1) or temp1 or temp2;temp0=(a(1) or b(1);temp1=temp0 and (a(0) and b(0);temp2=(a(1) or b(1)and(a(0)or b(0)and cin;c3=(a(2) and b
8、(2) or temp3 or temp4 or temp5;temp3=(a(2) or b(2)and(a(1) and b(1);temp4=(a(2) or b(2)and(a(1) or b(1)and (a(0) and b(0);temp5=(a(2) or b(2)and(a(1) or b(1)and(a(0) or b(0)and cin;g=(a(3) and b(3) or (a(3) or b(3) and (a(2) and b(2) or (a(3) or b(3) and temp3) or (a(3) or b(3) and temp4);p=(a(3) or
9、 b(3) and (a(2) or b(2) and (a(1) or b(1) and (a(0) or b(0);end behave; 16位加法器：LIBRARY ieee;USE ieee.std_logic_1164.ALL;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;ENTITY adder16 ISPORT ( a : IN std_logic_vector(15 DOWNTO 0); b : IN std_logic_vector(15 DOWNTO 0); cin : IN std_logic;
10、 sum : OUT std_logic_vector(15 DOWNTO 0); cout : OUT std_logic);END adder16;ARCHITECTURE behave OF adder16 IScomponent add4 PORT ( a : IN std_logic_vector(3 DOWNTO 0); b : IN std_logic_vector(3 DOWNTO 0); cin : IN std_logic; sum : OUT std_logic_vector(3 DOWNTO 0); g,p : OUT std_logic);end component;
11、signal g0,g1,g2,g3:std_logic;signal p0,p1,p2,p3:std_logic;signal c4,c8,c12:std_logic;beginu1:add4 port map(a(3 downto 0),b(3 downto 0),cin,sum(3 downto 0),g0,p0);u2:add4 port map(a(7 downto 4),b(7 downto 4),c4,sum(7 downto 4),g1,p1);u3:add4 port map(a(11 downto 8),b(11 downto 8),c8,sum(11 downto 8),
12、g2,p2);u4:add4 port map(a(15 downto 12),b(15 downto 12),c12,sum(15 downto 12),g3,p3);c4=g0 or(p0 and cin);c8=g1 or (p1 and g0) or (p1 and p0 and cin);c12=g2 or (p2 and g1) or (p2 and p1 and g0) or (p2 and p1 and p0 and cin);cout=g3 or (p3 and g2) or (p3 and p2 and g1) or(p3 and p2 and p1 and g0) or (p3 and p2 and p1 and p0 and cin);end behave;5.参考程序如下：1）同步置位/复位的D触发器。library ieee; use ieee.std_logic_1164.all; entity sync_rsdff is po
