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与门Library ieee;Use ieee.std_logic_1164.all;Entity an isPort(d1,d2 : in std_logic;op : out std_logic);End an;Architecture m1 of an isBeginop= 1 when(d1= 1 and d2= 1)else 0;End m1;或门Library ieee;Use ieee.std_logic_1164.all;Entity oor isPort(d1,d2 : in std_logic;op : out std_logic);End oor;Architecture m1 of oor isBeginop=0 when(d1=0 and d2=0)else1;End m1;非门Library ieee;Use ieee.std_logic_1164.all;Entity nt isPort(d1: in std_logic; op : out std_logic);End nt;Architecture m1 of nt isBeginop=0when(d1=1 )else1;End m1;
