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1、SOLUTIONS MANUAL COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE SEVENTH EDITION WILLIAM STALLINGS Copyright 2005: William Stallings 2005 by William Stallings All rights reserved. No part of this document may be reproduced, in any form or by any means, or posted on the Internet, wit
2、hout permission in writing from the author. NOTICE This manual contains solutions to all of the review questions and homework problems in Computer Organization and Architecture, Seventh Edition. If you spot an error in a solution or in the wording of a problem, I would greatly appreciate it if you w
3、ould forward the information via email to . An errata sheet for this manual, if needed, is available at WilliamS W.S. TABLE OF CONTENTS Chapter 2:Computer Evolution and Performance5 Chapter 3:Computer Function and Interconnection.9 Chapter 4:Cache Memory14 Chapter 5:Internal Memory27 Chapter 6:Exter
4、nal Memory33 Chapter 7:Input/Output37 Chapter 8:Operating System Support43 Chapter 9:Computer Arithmetic48 Chapter 10:Instruction Sets: Characteristics and Functions61 Chapter 11:Instruction Sets: Addressing Modes and Formats.72 Chapter 12:Processor Structure and Function .77 Chapter 13:Reduced Inst
5、ruction Set Computers (RISCs)83 Chapter 14:Instruction-Level Parallelism and Superscalar Processors87 Chapter 15:The IA-64 Architecture.93 Chapter 16:Control Unit Operation.97 Chapter 17:Microprogrammed Control.100 Chapter 18:Parallel Processing103 Appendix A:Number Systems.112 Appendix B:Digital Lo
6、gic.113 A A A A NSWERSNSWERSNSWERSNSWERS TOTOTOTO Q QQ QUESTIONSUESTIONSUESTIONSUESTIONS 2.1 In a stored program computer, programs are represented in a form suitable for storing in memory alongside the data. The computer gets its instructions by reading them from memory, and a program can be set or
7、 altered by setting the values of a portion of memory. 2.2 A main memory, which stores both data and instructions: an arithmetic and logic unit (ALU) capable of operating on binary data; a control unit, which interprets the instructions in memory and causes them to be executed; and input and output
8、(I/O) equipment operated by the control unit. 2.3 Gates, memory cells, and interconnections among gates and memory cells. 2.4 Moore observed that the number of transistors that could be put on a single chip was doubling every year and correctly predicted that this pace would continue into the near f
9、uture. 2.5 Similar or identical instruction set: In many cases, the same set of machine instructions is supported on all members of the family. Thus, a program that executes on one machine will also execute on any other. Similar or identical operating system: The same basic operating system is avail
10、able for all family members. Increasing speed: The rate of instruction execution increases in going from lower to higher family members. Increasing Number of I/O ports: In going from lower to higher family members. Increasing memory size: In going from lower to higher family members. Increasing cost
11、: In going from lower to higher family members. 2.6 In a microprocessor, all of the components of the CPU are on a single chip. A A A A NSWERSNSWERSNSWERSNSWERS TOTOTOTO P P P P ROBLEMSROBLEMSROBLEMSROBLEMS 2.1 This program is developed in HAYE98. The vectors A, B, and C are each stored in 1,000 con
12、tiguous locations in memory, beginning at locations 1001, 2001, and 3001, respectively. The program begins with the left half of location 3. A counting variable N is set to 999 and decremented after each step until it reaches 1. Thus, the vectors are processed from high location to low location. CHA
13、PTER 2 COMPUTER EVOLUTION AND PERFORMANCE LocationInstructionComments 0999Constant (count N) 11Constant 21000Constant 3LLOAD M(2000)Transfer A(I) to AC 3RADD M(3000)Compute A(I) + B(I) 4LSTOR M(4000)Transfer sum to C(I) 4RLOAD M(0)Load count N 5LSUB M(1)Decrement N by 1 5RJUMP+ M(6, 20:39)Test N and
14、 branch to 6R if nonnegative 6LJUMP M(6, 0:19)Halt 6RSTOR M(0)Update N 7LADD M(1)Increment AC by 1 7RADD M(2) 8LSTOR M(3, 8:19)Modify address in 3L 8RADD M(2) 9LSTOR M(3, 28:39)Modify address in 3R 9RADD M(2) 10LSTOR M(4, 8:19)Modify address in 4L 10RJUMP M(3, 0:19)Branch to 3L 2.2 a. OpcodeOperand
15、00000001000000000010 b. First, the CPU must make access memory to fetch the instruction. The instruction contains the address of the data we want to load. During the execute phase accesses memory to load the data value located at that address for a total of two trips to memory. 2.3 To read a value f
16、rom memory, the CPU puts the address of the value it wants into the MAR. The CPU then asserts the Read control line to memory and places the address on the address bus. Memory places the contents of the memory location passed on the data bus. This data is then transferred to the MBR. To write a value to memory, the CPU puts the address of the value it wants to write into the MAR. The CPU also places the data it wants to write into the MBR. The CPU then asserts t
